SoC Engineering, Principal Engineer

Synopsys Inc; Sunnyvale (CA); On-site; USD 220,000 - 320,000; Full time

Job summary

Synopsys Inc. in Sunnyvale seeks a senior design leader to drive ASIC/FPGA programs from spec to silicon. You will lead teams, craft micro-architectures, and push for high-performance, low-power outcomes across automotive, aerospace, and HPC markets.

You’ll mentor engineers, resolve timing and CDC issues, and work directly with customers to translate requirements into robust turnkey designs using SystemVerilog and industry protocols.

Qualifications

• Bachelor's degree in Electrical Engineering or Computer Engineering.
• 15+ years designing and verifying ASIC/FPGA through multiple tape-outs or production releases.
• Proven experience leading design teams and mentoring engineers.
• Deep understanding of the full ASIC design flow from micro-architecture to handoff.
• Strong SystemVerilog RTL coding skills and ability to review complex control/datapath logic.
• Experience with PCIe, Ethernet, or UCIe in production designs.

Responsibilities

• Lead design teams through full ASIC and FPGA development cycles, from specification to GDSII handoff.
• Partition and architect complex SOC designs from customer requirements, balancing performance, area, and power.
• Drive RTL development using SystemVerilog, ensuring quality through reviews, lint checks, CDC/RDC analysis, and synthesis readiness.
• Collaborate with verification, DFT, and physical design teams to resolve integration issues and timing closures.
• Implement complex industry-standard protocols including PCIe, Ethernet, and UCIe within SOC designs.
• Develop and refine ASIC design flows and methodologies using Synopsys and vendor tools for simulation, synthesis, static timing analysis, and signoff.
• Work hands-on with customers across automotive, aerospace, defense, and HPC markets.

Skills

SystemVerilog RTL

Leadership

ASIC/FPGA design

Timing closure

Clock domain crossing

PCIe/Ethernet/UCIe protocols

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Tools

Simulators

Lint tools

CDC/RDC checkers

Synthesis tools

STA platforms

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years turning complex system requirements into working silicon, and you know that the hardest part is not writing RTL, it is making the right architectural decisions in week two that keep your team from hitting a wall in month six. You have led design teams through the full cycle, from early partitioning conversations to timing closure, and you understand that leadership at this level means knowing when to dive into the details and when to step back and let your engineers solve it.

You are the engineer who can sit with a customer discussing SoC requirements and walk out with a micro-architecture that your team can actually build. Ambiguity does not slow you down. You ask the right questions, make decisions with incomplete information, and adjust as new constraints emerge. You have debugged enough CDC violations and timing paths to know what good RTL looks like before it even hits synthesis.

You care about the people you lead. Not in a vague mentorship way, but in the practical sense of unblocking a senior engineer stuck on a clock domain crossing issue or helping a junior designer understand why their FSM will not synthesize cleanly. At Synopsys, you will work on real customer designs that ship in high-performance computing, automotive, and aerospace systems, leading teams that build ASICs and FPGAs that actually matter.

What You'll Be Doing

• Lead design teams of junior and senior engineers through full ASIC and FPGA development cycles, from specification to GDSII handoff
• Partition and architect complex SOC designs from customer requirements, creating high-level and micro-architectures that balance performance, area, and power
• Drive RTL development using SystemVerilog, ensuring designs meet quality standards through code reviews, lint checks, CDC/RDC analysis, and synthesis readiness
• Collaborate directly with verification, DFT, and physical design teams to resolve integration issues, timing closure challenges, and design-for-test requirements
• Implement complex industry-standard protocols including PCIe, Ethernet, and UCIe within customer-specific SOC designs
• Develop and refine ASIC design flows and methodologies using Synopsys and vendor tools for simulation, synthesis, static timing analysis, and signoff
• Work hands-on with customers ranging from startups to industry leaders across automotive, aerospace, defense, and high-performance computing markets

The Impact You Will Have

• Your architectural decisions will directly determine whether customer designs meet aggressive PPA targets in advanced process nodes
• The teams you build and lead will deliver turnkey SOC designs that power next-generation AI, autonomous vehicles, and mission-critical aerospace systems
• Your design methodologies will become reusable frameworks that accelerate future customer engagements across the Solutions group
• The RTL quality standards you enforce will reduce verification cycles and prevent costly respins for multi-million-dollar tape-outs
• Your ability to navigate complex customer requirements will unlock new business opportunities and long-term partnerships
• The engineers you mentor will grow into technical leaders who carry forward the rigor and craft you bring to every design
• Your work will help Synopsys customers ship products faster, with higher confidence, in markets where failure is not an option

What You'll Need

• Bachelor's degree in Electrical Engineering or Computer Engineering
• 15+ years of hands-on experience designing and verifying ASIC or FPGA devices through multiple tape-outs or production releases
• Proven experience leading design teams, including mentoring engineers and managing technical execution across project milestones
• Deep understanding of the full ASIC design flow from micro-architecture through RTL development, synthesis, timing closure, and physical design handoff
• Strong SystemVerilog RTL coding skills with demonstrated ability to design and review complex control and datapath logic
• Working knowledge of industry-standard protocols such as PCIe, Ethernet, or UCIe in real production designs
• Experience with ASIC development tools including simulators, lint tools, CDC/RDC checkers, synthesis tools, and static timing analysis platforms

Who You Are

• You can explain a complex clock domain crossing issue to a junior engineer in a way that makes them understand the underlying problem, not just the fix
• You have strong opinions on RTL coding style and design partitioning, and you can defend them with specific examples from designs you have shipped
• You are comfortable pushing back on a customer requirement when the architecture does not make sense, and you can propose a better solution that still meets their goals
• You move between leading strategy conversations and debugging synthesis warnings without losing context or momentum
• You treat code reviews as teaching moments, not checklists, and your feedback makes engineers better at their craft
• You know when a design is ready to move forward and when it needs another iteration, and you are not afraid to make that call even under schedule pressure

The Team You'll Be Part Of

You will join the Synopsys Solutions group, a team that delivers end-to-end SOC design services to customers across high-performance computing, automotive, aerospace, and defense markets. Your team works on full turnkey designs from specification to silicon, partnering with customers that range from startups to industry leaders and government agencies. You will collaborate closely with verification, DFT, and physical design teams, and you will have access to the full Synopsys EDA toolset and IP portfolio to solve customer challenges.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.