Sr. Staff Design Verification Engineer

Socket.dev; San Jose (CA); Hybrid; USD 140,000 - 190,000; Full time

Benefits offered by this job

Benefits at a glance

Job summary

AMD in San Jose, CA is hiring a SMTS Silicon Design Engineer to work in front-end design/integration, collaborating with architecture, IP design, and Physical Design teams to achieve first pass silicon success. The role emphasizes DFT implementation, scan insertion, ATPG generation, and post-silicon support for yield learning.

The candidate should have strong accuracy, communication, and problem-solving skills, plus experience with DFT methodologies and related EDA tools.

Qualifications

• Design for Test methodologies and DFT verification experience (IEEE1500, JTAG 1149.x, Scan, memory BIST).
• Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX.
• Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design.

Responsibilities

• Implementation and verification of DFT architecture and features
• Scan insertion and ATPG pattern generation
• ATPG patterns verification with gate-level simulation
• Test coverage and test cost reduction analysis
• Post silicon support to ensure successful bring up and enhance yield learning

Skills

DFT verification

Scan insertion

ATPG

Gate-level simulation

Verilog RTL design

IEEE1500

JTAG 1149.x

memory BIST

Perl/Shell scripting

Education

Bachelor's or master's degree in computer engineering/Electrical Engineering

Tools

Mentor testkompress

Synopsys Tetramax/DFTMAX

VCS

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re redesigning next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger— technology that moves the world forward. Join us and, together, we’ll advance your career.

SMTS SILICON DESIGN ENGINEER

THE ROLE

As a member of the Radeon Technologies Group, you will help bring to life cutting‑edge designs. As a member of the front‑end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

THE PERSON

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail‑oriented, possessing good communication and problem‑solving skills.

KEY RESPONSIBILITIES

• Implementation and verification of DFT architecture and features
• Scan insertion and ATPG pattern generation
• ATPG patterns verification with gate-level simulation
• Test coverage and test cost reduction analysis
• Post silicon support to ensure successful bring up and enhance yield learning

PREFERRED EXPERIENCE

• Understanding of Design for Test methodologies and DFT verification experience (e.g. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.)
• Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX
• Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design

ACADEMIC CREDENTIALS

• Bachelor's or master's degree in computer engineering/Electrical Engineering

LOCATION

San Jose, CA (Hybrid)

#LI-MV1

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.