Sr. Staff Silicon Development Engineer

Socket.dev; San Jose (CA); Hybrid; USD 120,000 - 180,000; Full time

Job summary

AMD in San Jose, CA is seeking a DFT engineer to implement and verify DFT architectures and features. You will perform scan insertion, ATPG pattern generation, and gate-level ATPG verification, contributing to post-silicon yield learning.

The candidate should have hands-on experience with DFT methodologies, Mentor Testkompress or Synopsys Tetramax/DFTMAX, and Verilog RTL design, with strong problem-solving and communication skills.

Qualifications

• Understanding of Design for Test methodologies and DFT verification experience (IEEE1500, JTAG 1149.x, Scan, memory BIST).
• Experience with Mentor Testkompress and/or Synopsys Tetramax/DFTMAX.
• Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design.

Responsibilities

• Implementation and verification of DFT architecture and features
• Scan insertion and ATPG pattern generation
• ATPG patterns verification with gate-level simulation
• Test coverage and test cost reduction analysis; post-silicon support to ensure successful bring up and yield learning

Skills

IEEE1500 / JTAG / Scan / memory BIST

Education

Bachelor's or master's in Computer/Electrical Engineering

Tools

Mentor Testkompress

Synopsys Tetramax/DFTMAX

VCS

Perl/Shell scripting

Verilog RTL design

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward.Join us and, together, we’ll advance your career.

THE ROLE:

As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

THE PERSON:

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBILITIES:

• Implementation and verification of DFT architecture and features
• Scan insertion and ATPG pattern generation
• ATPG patterns verification with gate-level simulation
• Test coverage and test cost reduction analysisPost silicon support to ensure successful bring up and enhance yield learning

PREFERRED EXPERIENCE:

• Understanding of Design for Test methodologies and DFT verification experience (e.g. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.)
• Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX
• Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design

ACADEMIC CREDENTIALS:

• Bachelor's or master's degree in computer engineering/Electrical Engineering

LOCATION:

San Jose, CA (Hybrid)

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.