Senior DFT Design Engineer for SoC/ASIC Test Excellence

Cadence; Austin (TX); On-site; USD 140,000 - 210,000; Full time

Job summary

Cadence is seeking a SoC/ASIC Digital Design Engineer with extensive experience in Design for Test (DFT). The role emphasizes scan chain insertion, compression scan technologies, MBIST, and ATPG pattern generation, with a preference for hands-on synthesis, verification, and debugging Verilog test benches.

US citizenship is preferred. Ideal candidates will have deep knowledge of DFT insertion flows, JTAG 1149.1/6, IEEE1500/IEEE1687, and the ability to work independently in a fast-paced project

Qualifications

• 10-20 years of professional experience in SoC/ASIC Digital Design with focus on DFT.
• Intimate knowledge of DFT insertion flows.
• Experience with compression scan insertion, LBIST and other scan technologies.
• Expertise in ATPG to achieve design test coverage goals.
• Debug and analysis of failures to improve fault coverage.
• Verification of ATPG testbenches and debugging root causes of simulation mis-compares.

Skills

DFT design

ATPG

MBIST

Synthesis and verification

JTAG 1149.1/6

Tools

Cadence tools

Synthesis tools

Verilog testbenches

Job description

Cadence is seeking a SoC/ASIC Digital Design Engineer with extensive experience in Design for Test (DFT). The role emphasizes scan chain insertion, compression scan technologies, MBIST, and ATPG pattern generation, with a preference for hands-on synthesis, verification, and debugging Verilog test benches.

US citizenship is preferred. Ideal candidates will have deep knowledge of DFT insertion flows, JTAG 1149.1/6, IEEE1500/IEEE1687, and the ability to work independently in a fast-paced project