Senior DFT Engineer | California (Onsite)

MosChip Technologies; Santa Clara (CA); On-site; USD 124,000 - 179,000; Part time

Job summary

MosChip Technologies is seeking a Senior DFT Engineer for onsite work in the California Bay Area. You will drive the DFT implementation and verification for complex SoC/ASIC designs, covering scan, ATPG, MBIST, and silicon bring-up activities with hands-on debugging and cross-team collaboration.

The role requires 3–8 years in DFT, strong scripting abilities in TCL/Perl, and experience with Tessent and other major EDA tools. Excellent communication and teamwork are essential.

Qualifications

• 3–8 years of DFT experience in SoC/ASIC designs
• Strong experience with Scan, Compression, ATPG, JTAG, and Boundary Scan
• MBIST implementation, verification, and Memory Repair (BIRA/BISR)
• Experience with hierarchical SoC DFT implementation and verification
• Familiarity with DFT simulations, SDF timing simulations, and debugging timing constraints
• Experience with Tessent EDA tools is a must
• Strong debugging, problem-solving, communication, and teamwork skills

Responsibilities

• Support implementation and verification of DFT solutions for complex SoC/ASIC designs.
• Work across the full DFT flow from scan implementation through ATPG, MBIST, and silicon bring-up activities.

Skills

DFT engineering

ATPG

MBIST

JTAG

Boundary Scan

Memory Repair

Scripting TCL

Perl scripting

5nm tape-out

Debugging

Communication

Teamwork

Tools

Siemens Tessent

Synopsys

Cadence

Tessent EDA tools

Job description

Senior DFT Engineer | California (Onsite)

We are looking for a Senior DFT Engineer to support the implementation and verification of DFT solutions for complex SoC/ASIC designs. The ideal candidate will have hands-on experience across the full DFT flow, from scan implementation through ATPG, MBIST, and silicon bring-up activities.

Key Requirements:

• 3 to 8 years of experience in DFT for SoC/ASIC designs
• Strong experience with Scan, Compression, ATPG, JTAG, and Boundary Scan
• Hands-on experience with MBIST implementation, verification, and Memory Repair (BIRA/BISR)
• Experience with hierarchical SoC DFT implementation and verification
• Familiarity with DFT simulations, SDF timing simulations, and debugging timing constraints
• Experience with industry-standard DFT tools such as Siemens Tessent, Synopsys, or Cadence tool suites
• Scripting skills in TCL and/or Perl
• Experience with successful SoC/ASIC tape outs, preferably at advanced technology nodes (5nm or below)
• Strong debugging, problem-solving, communication, and teamwork skills
• Experience with Tessent EDA tools is a must

Location:

Bay Area, CA

Work Authorization:

Green Card & US citizens

Employment Type:

1099 contract.