Signal & Power Integrity Engineer, Annapurna Labs - AI Silicon Packaging

Annapurna Labs (U.S.) Inc.; Austin (TX); On-site; USD 130,000 - 185,000; Full time

Job summary

Annapurna Labs, an organization within Amazon, seeks a Signal or Power Integrity Engineer to join our hardware team in Austin, TX. You will perform package-level SI/PI analyses for advanced 2.5D/3D-IC packaging and collaborate with die and board teams to optimize performance and reliability.

You will build models, run high-speed simulations, and help decisions across IC, package, and board boundaries. Strong EM experience and packaging knowledge are essential for success.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 5+ years of experience in signal integrity, power integrity, or package design.
• Solid understanding of SI or PI with working awareness of the other.
• Experience with EM simulation and SI/PI tools such as HFSS, Cadence Sigrity, ADS.
• Understanding of advanced packaging technologies: 2.5D/3D-IC, interposers, RDL, TSVs.

Responsibilities

• Perform package-level SI or PI simulations for 2.5D, 3D-IC, fan-out, and interposers.
• Support package stack-up design: dielectric evaluation, impedance control, layer assignment, RDL routing.
• Run high-speed channel simulations (S-parameters, time-domain, eye diagrams) for interfaces.
• Model advanced interconnects: microbumps, TSVs, microvias, RDL traces for signal or power paths.
• Build/validate models for decoupling technologies like on-die capacitance, DTCs, IPD capacitors.
• Coordinate with SoC die-level and board design teams to co-optimize package architecture.
• Flag packaging risks (warpage, via reliability, impedance variation) and propose mitigations.

Skills

Signal integrity

Power integrity

Package design

EM simulation

S-parameter extraction

Crosstalk

Return loss

Channel analysis

2.5D/3D-IC packaging

Interposers

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

HFSS

Cadence Sigrity (PowerSI, PowerDC, Clarity)

ADS

Job description

Annapurna Labs (our organization within Amazon) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago-even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.

We are seeking a Signal or Power Integrity Engineer to join our hardware team and contribute to SI/PI analysis and optimization of advanced packaging solutions for next-generation machine learning and data center ASICs.

In this role, you will support the package-level signal or power integrity effort - performing detailed simulations, building models, and contributing to design decisions across IC, package, and board boundaries. You'll work closely with senior engineers to help ensure our advanced packaging technologies meet performance, power delivery, and manufacturing targets.

Key job responsibilities

• Perform package-level SI or PI simulations for 2.5D, 3D-IC, fan-out, and silicon interposer/bridge architectures under guidance from senior engineers.
• Support package stack-up design: assist with dielectric material evaluation, impedance control analysis, layer assignment, and RDL routing studies.
• Run high-speed channel simulations (S-parameter extraction, time-domain analysis, eye diagrams) for die-to-die and die-to-board interfaces, or analyze package PDN performance (decoupling effectiveness, plane resonance, IR drop, AC impedance).
• Model advanced interconnects: microbumps, C4 bumps, TSVs, microvias, PTH vias, and RDL traces for signal or power paths.
• Build and validate models for decoupling technologies such as on-die capacitance, deep trench capacitors (DTCs), or IPD capacitors as needed.
• Coordinate with SoC die-level teams and board design teams to gather requirements and support co-optimization of package architecture.
• Flag potential package manufacturing risks - warpage, via reliability, impedance variation - and propose mitigation approaches.

A day in the life

Our team is dedicated to supporting new members. We have a broad mix of experience levels and tenures, and we're building an environment that celebrates knowledge-sharing and mentorship. Our senior members enjoy one-on-one mentoring and thorough, but kind, code reviews. We care about your career growth and strive to assign projects that help our team members develop your engineering expertise so you feel empowered to take on more complex tasks in the future.

Diverse Experiences

Amazon values diverse experiences. Even if you do not meet all of the qualifications and skills listed in the job description, we encourage candidates to apply. If your career is just starting, hasn't followed a traditional path, or includes alternative experiences, don't let it stop you from applying.

Inclusive Team Culture

Here at Amazon, it's in our nature to learn and be curious. Our employee-led affinity groups foster a culture of inclusion that empower us to be proud of our differences. Ongoing events and learning experiences, including our Conversations on Race and Ethnicity (CORE) and AmazeCon (gender diversity) conferences, inspire us to never stop embracing our uniqueness.

Work/Life Balance

We value work-life harmony. Achieving success at work should never come at the expense of sacrifices at home, which is why we strive for flexibility as part of our working culture. When we feel supported in the workplace and at home, there's nothing we can't achieve in the cloud.

Basic Qualifications

• Bachelor's degree in Electrical Engineering or a related field
• 5+ years of experience in signal integrity, power integrity, or package design
• Solid understanding of either SI (S-parameter extraction, crosstalk, return loss, channel analysis) or PI (PDN impedance analysis, IR drop, decoupling strategy), with working awareness of the other
• Experience with EM simulation and SI/PI tools such as HFSS, Cadence Sigrity (PowerSI, PowerDC, Clarity), ADS, or equivalent
• Understanding of advanced packaging technologies: 2.5D/3D-IC, silicon interposers, fan-out wafer-level packaging, RDL, TSVs, and microbump interconnects
• Familiarity with stack-up design and impedance control for multi-layer organic substrates or silicon interposers.
• Good communication skills with the ability to participate in technical discussions across silicon, package, and board teams

Preferred Qualifications

• Master's degree in Electrical Engineering or a related field
• 3+ years in signal integrity, power integrity, or package design
• Exposure to high-speed serial protocols (PCIe, UCIe, or custom SerDes) at the package level
• Experience correlating SI/PI simulations with lab measurements (TDR, VNA, oscilloscope)
• Familiarity with equalization techniques (DFE, CTLE, FFE) or PDN target impedance methodology
• Interest or experience in package co-design methodologie