Senior SI/PI Package Lead – 2.5D/3D ICs

Amazon Inc.; Austin (TX); On-site; USD 241,000 - 326,000; Full time

Job summary

Amazon in Austin, TX is seeking a Senior Manager of Package Signal & Power Integrity to lead a focused SI/PI team and set the technical direction for 2.5D/3D packaging. You will drive PDN/PI strategies across die-to-die interfaces and high-speed SerDes, while staying hands-on with modeling and post-silicon correlation.

You will partner with silicon design, OSATs, substrate teams, and system architects to ensure robust signaling and power delivery for next-generation chiplet products.

Qualifications

• Advanced degree with strong background in electromagnetics, signal integrity, or microelectronics.
• Proven track record in SI/PI engineering for semiconductor packaging.
• Experience leading SI/PI or packaging teams.

Responsibilities

• Lead and develop a team of SI/PI engineers, setting priorities and career growth.
• Define and execute SI/PI design methodology for 2.5D/3D packages.
• Drive end-to-end SI/PI analysis for high-speed interfaces and HBM/PCIe SerDes.
• Own PDN design and sign-off across die, interposer, substrate, and PCB.
• Develop channel models and BER/eye-diagram analyses for multi-lane links.
• Establish SI/PI guidelines, sign-off criteria, and automation flows.
• Collaborate with ASIC, PHY/IP, package layout, thermal/mechanical, PCB, and system teams.
• Lead post-silicon validation and model-to-hardware correlation.

Skills

Signal Integrity

Power Integrity

People management

2.5D/3D packaging

PDN design

PCB/interposer knowledge

Python/MATLAB scripting

Education

Master's in Electrical Engineering

PhD in Electrical Engineering

Tools

Ansys HFSS

Cadence Sigrity

Keysight ADS

Job description

Amazon in Austin, TX is seeking a Senior Manager of Package Signal & Power Integrity to lead a focused SI/PI team and set the technical direction for 2.5D/3D packaging. You will drive PDN/PI strategies across die-to-die interfaces and high-speed SerDes, while staying hands-on with modeling and post-silicon correlation.

You will partner with silicon design, OSATs, substrate teams, and system architects to ensure robust signaling and power delivery for next-generation chiplet products.