Senior Manager, Package SI/PI & 3D Chiplet Systems

Annapurna Labs; Cupertino (CA); On-site; USD 277,000 - 350,000; Full time

Job summary

Annapurna Labs is seeking a Senior Manager to lead a SI/PI team focused on 2.5D/3D packaging for next-generation chiplet platforms. You will set the technical direction for package-level SI/PI across CoWoS, EMIB, and 3D die-stacking, while remaining hands-on with modeling, simulation, and post-silicon correlation.

You will own the SI/PI strategy from architecture through production, partnering with silicon design, physical design, system architecture, and OSAT vendors to ensure robust signaling

Qualifications

• MS or PhD in Electrical Engineering with emphasis in electromagnetics, signal integrity, power integrity, or microelectronics.
• 12+ years of progressive SI/PI engineering experience in semiconductor packaging.
• 3+ years of direct people-management experience leading SI/PI or packaging engineering teams.
• Expertise in 2.5D/3D advanced packaging technologies (CoWoS-S/L/R, EMIB, Foveros, 3D die stacking, TSV, RDL).
• Hands-on SI/PI analysis for high-speed SerDes interfaces at 56G NRZ / 112G+ PAM4 rates.
• HBM3/4 SI/PI design and timing budget methodology.
• PCIe Gen5/Gen6 channel design, compliance, and sign-off.
• Working knowledge of UCIe standards for chiplet interconnects.
• Proficiency in EDA/simulation tools and scripting for automation.
• Ability to drive cross-functional alignment across silicon, package, board, and system teams.

Responsibilities

• Lead and develop a team of SI/PI engineers, setting priorities and career growth.
• Define and execute SI/PI design methodology for 2.5D/3D IC packages.
• Perform end-to-end SI/PI analysis and optimization for high-speed interconnects.
• Own PDN design and sign-off across die, interposer, substrate, and PCB.
• Develop and validate channel models and BER/eye-diagram analyses.
• Establish SI/PI design guidelines, sign-off criteria, and automation flows.
• Collaborate with ASIC, PHY/IP, package layout, thermal/mechanical, PCB, and system teams.
• Lead post-silicon validation and model-to-hardware correlation.

Skills

Team leadership

SI/PI design

2.5D/3D packaging

HBM3/4 SI/PI

PCIe Gen5/Gen6/Gen7

UCIe

EDA tools

Python/MATLAB/Tcl

S-parameter/IBIS-AMI

Cross-functional alignment

Education

MS or PhD in Electrical Engineering

Tools

Ansys HFSS

HFSS/SIwave/Q3D

Cadence Sigrity (PowerSI/SystemSI)

Keysight ADS

HSPICE/Spectre

Job description

Annapurna Labs is seeking a Senior Manager to lead a SI/PI team focused on 2.5D/3D packaging for next-generation chiplet platforms. You will set the technical direction for package-level SI/PI across CoWoS, EMIB, and 3D die-stacking, while remaining hands-on with modeling, simulation, and post-silicon correlation.

You will own the SI/PI strategy from architecture through production, partnering with silicon design, physical design, system architecture, and OSAT vendors to ensure robust signaling