Senior SI/PI Manager for 3D Packaging

Annapurna Labs; Austin (TX); On-site; USD 241,000 - 326,000; Full time

Job summary

Annapurna Labs in Austin, TX seeks a Senior Manager of Package Signal & Power Integrity to lead a small SI/PI team and set the technical direction for 2.5D/3D packaging platforms including CoWoS and EMIB. You will remain hands-on with modeling, simulation, and post-silicon correlation while owning the SI/PI strategy from architecture to production.

The role requires 12+ years in SI/PI within semiconductor packaging, with 3+ years of people management, and strong proficiency in 2.5D/3D packaging,

Qualifications

• MS or PhD in Electrical Engineering, with emphasis in electromagnetics, signal integrity, power integrity, or microelectronics.
• 12+ years of progressive SI/PI engineering experience in semiconductor packaging (IC package, interposer, or substrate design).
• 3+ years of direct people-management experience leading SI/PI or packaging engineering teams.
• Demonstrated expertise in 2.5D/3D advanced packaging technologies (CoWoS-S/L/R, EMIB, Foveros, 3D die stacking, TSV, RDL).
• Hands-on experience with SI/PI analysis for high-speed SerDes interfaces at 56G NRZ / 112G+ PAM4 data rates.
• Strong background in HBM3/4 SI/PI design and timing budget methodology (HBM3/HBM3E/HBM4 or newer).
• Experience with PCIe Gen5/Gen6 channel design, compliance, and sign-off at the package and system level.
• Working knowledge of UCIe or comparable die-to-die interconnect standards for chiplet architectures.
• Proficiency in industry EDA/simulation tools: Ansys HFSS/SIwave/Q3D, Cadence Sigrity (PowerSI, SystemSI), Keysight ADS, HSPICE/Spectre.
• Strong scripting skills (Python, MATLAB, Tcl) for simulation automation and data analysis.
• Proven ability to drive cross-functional alignment across silicon, package, board, and system teams in a fast-paced product environment.

Responsibilities

• Lead and develop a team of SI/PI engineers, setting priorities, driving career growth, and building world-class packaging expertise.
• Define and execute SI/PI design methodology for 2.5D/3D IC packages—including silicon interposer, RDL, TSV, and bridge-based architectures.
• Drive chip-package-system co-design by performing end-to-end SI/PI analysis and optimization for HBM (HBM3/HBM3E+), PCIe Gen5/Gen6/Gen7, UCIe die-to-die interconnects and high-speed SerDes (112G+/224G PAM4).
• Own PDN design and sign-off across die, interposer, package substrate, and PCB, including AC/DC/transient droop analysis and decoupling strategy.
• Develop and validate channel models (S-parameter, IBIS-AMI) and perform BER/eye-diagram analysis for multi-lane high-speed links.
• Establish SI/PI design guidelines, sign-off criteria, and automation flows; drive continuous improvement in accuracy and productivity.
• Partner with ASIC architects, PHY/IP teams, package layout, thermal/mechanical, PCB, and system design teams to close electrical specifications.
• Collaborate with other internal partners and external partners (possible like foundry, OSAT, and substrate suppliers etc.) on technology assessment, DFM trade-offs, and new package platform enablement.
• Lead post-silicon validation and model-to-hardware correlation using VNA, TDR, oscilloscope, and spectrum analyzer measurements.

Skills

Team leadership

2.5D/3D packaging

HBM/PI/PCIe

Scripting (Python/MATLAB/Tcl)

Cross-functional collaboration

Modeling/simulation

Education

MS/PhD in Electrical Engineering

Tools

Ansys HFSS/SIwave/SystemSI

Cadence Sigrity

Keysight ADS

HSPICE/Spectre

Job description

Annapurna Labs in Austin, TX seeks a Senior Manager of Package Signal & Power Integrity to lead a small SI/PI team and set the technical direction for 2.5D/3D packaging platforms including CoWoS and EMIB. You will remain hands-on with modeling, simulation, and post-silicon correlation while owning the SI/PI strategy from architecture to production.

The role requires 12+ years in SI/PI within semiconductor packaging, with 3+ years of people management, and strong proficiency in 2.5D/3D packaging,