AI Silicon Packaging SI/PI Engineer

Amazon Web Services (AWS); Austin (TX); On-site; USD 136,000 - 184,000; Full time

Job summary

Annapurna Labs (U.S.) Inc. in Austin, TX is seeking a Signal or Power Integrity Engineer to drive SI/PI analysis for advanced packaging in machine learning and data center ASICs. You will perform package-level simulations, build models, and support decisions across IC, package, and board boundaries.

You will collaborate with SoC die teams and board design, address PDN performance, and help mitigate risks while growing your expertise in a supportive environment.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 5+ years experience in signal integrity, power integrity, or package design.
• Solid understanding of SI or PI with awareness of the other.
• Experience with EM simulation and SI/PI tools (HFSS, Sigrity, ADS).
• Understanding of 2.5D/3D-IC packaging, interposers, RDL, TSVs.

Responsibilities

• Perform package-level SI or PI simulations for 2.5D, 3D-IC, fan-out, and interposers.
• Support package stack-up design, impedance control, and RDL routing studies.
• Run high-speed channel simulations and analyze die-to-board interfaces.
• Model advanced interconnects such as microbumps, TSVs, and RDL traces.
• Build and validate decoupling models (DTCs, IPD capacitors, on-die caps).
• Coordinate with SoC die and board teams for co-optimization.
• Flag manufacturing risks and propose mitigation approaches.

Skills

SI/PI analysis

EM simulation

S-parameter extraction

Power integrity analysis

HFSS

Cadence Sigrity PowerSI/PowerDC/Clairy

ADS

2.5D/3D-IC packaging

RDL routing

Strong communication

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

HFSS

Cadence Sigrity PowerSI/PowerDC/Clarity

ADS

Job description

Annapurna Labs (U.S.) Inc. in Austin, TX is seeking a Signal or Power Integrity Engineer to drive SI/PI analysis for advanced packaging in machine learning and data center ASICs. You will perform package-level simulations, build models, and support decisions across IC, package, and board boundaries.

You will collaborate with SoC die teams and board design, address PDN performance, and help mitigate risks while growing your expertise in a supportive environment.