Senior SerDes Architect for Next-Gen AI Interconnects

Celero Communications, Inc.; United States; Remote; USD 180,000 - 260,000; Full time

Job summary

Celero Communications, Inc. is seeking a Principal SerDes Design Engineer to architect and implement next‑generation SerDes for high-speed interconnects powering AI workloads.

The role involves system-level modeling, behavioral simulations, and leading lab validation in a state‑of‑the‑art lab. Ideal candidates hold a Master’s or PhD in EE with 10+ years of SerDes experience, proven tape-out success, and deep knowledge of 16nm–2nm processes.

Qualifications

• 10+ years in SerDes design with tape-out experience.
• Strong in lab bring-up, characterization, and debugging for production.
• Experience with advanced node technologies (16nm/12nm through 2nm).
• Cross-functional collaboration to deliver IP within SOCs.

Responsibilities

• Define architecture and topologies for next‑gen SerDes.
• Lead system-level modeling and jitter budgeting using MATLAB/Verilog-A.
• Design analog/mixed-signal blocks (CTLE, DFE, PLLs, DLLs, TDCs).
• Oversee layout to minimize parasitics and electromigration; validate SI/PI.

Skills

SerDes design

High speed signaling

SystemVerilog

MATLAB

Education

Master’s or PhD in Electrical Engineering

Tools

SystemVerilog

Verilog-A

MATLAB

Job description

Celero Communications, Inc. is seeking a Principal SerDes Design Engineer to architect and implement next‑generation SerDes for high-speed interconnects powering AI workloads.

The role involves system-level modeling, behavioral simulations, and leading lab validation in a state‑of‑the‑art lab. Ideal candidates hold a Master’s or PhD in EE with 10+ years of SerDes experience, proven tape-out success, and deep knowledge of 16nm–2nm processes.