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Cadence Design Systems, Inc. in San Jose seeks a Senior Engineer for the System Verification Group to advance the Xcelium RTL/logic simulator and tackle the next generation of AI and hyperscale chip designs.
You will design, optimize, and lead others in C++ development, RTL/Verilog knowledge, and SDC constraint handling, with a collaborative global team and a strong emphasis on performance.
Cadence Design Systems, Inc. in San Jose seeks a Senior Engineer for the System Verification Group to advance the Xcelium RTL/logic simulator and tackle the next generation of AI and hyperscale chip designs.
You will design, optimize, and lead others in C++ development, RTL/Verilog knowledge, and SDC constraint handling, with a collaborative global team and a strong emphasis on performance.