Senior Principal RTL Verification Architect

Cadence; San Jose (CA); On-site; USD 161,000 - 299,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Cadence is seeking a Senior Engineer in the System Verification Group in California to advance Xcelium RTL/logic simulation for next‑gen hardware verification. You will architect features, optimize performance in C/C++, and collaborate with a distributed team to deliver high‑quality results.

You will apply deep knowledge of RTL/logic simulation, SDC constraints, and timing analysis, while contributing to robust unit tests and specifications in a fast‑moving environment.

Qualifications

• MS/PhD in Computer Science or Electrical Engineering required or MS/EE with extensive industry experience.
• 5+ years of experience in EDA software development.
• Strong RTL/Logic Simulation and SDC constraints knowledge with Timing Analysis focus.

Responsibilities

• Enhance and support Xcelium RTL/logic simulator engine with new features.
• Enhance Timing Constraints Verification technology inside Xcelium.
• Design and optimize graph algorithms for SDC constraints on large graphs.
• Analyze bottlenecks and optimize C/C++ code for faster compilation and smaller memory footprint.
• Collaborate with global team to deliver high-quality results.
• Write specifications and unit tests for code.

Skills

RTL/Logic Simulation

SDC constraints

Timing Analysis

C/C++

SystemVerilog/Verilog

Multi-threaded programming

Education

MS/PhD in Computer Science or Electrical Engineering

Job description

Cadence is seeking a Senior Engineer in the System Verification Group in California to advance Xcelium RTL/logic simulation for next‑gen hardware verification. You will architect features, optimize performance in C/C++, and collaborate with a distributed team to deliver high‑quality results.

You will apply deep knowledge of RTL/logic simulation, SDC constraints, and timing analysis, while contributing to robust unit tests and specifications in a fast‑moving environment.