Senior RTL Design & Verification Engineer — AI-Driven EDA

ScOp Venture Capital LLC.; Santa Barbara, Northern (CA, KY); Hybrid; USD 140,000 - 190,000; Full time

Benefits offered by this job

Competitive salary

Equity

Benefits

Growth opportunities

Job summary

ChipAgents in Santa Barbara, CA, is seeking a Senior Design and Verification Engineer to join our core product and research team. You will collaborate with AI engineers to build agentic AI systems for EDA and shape how engineers think about RTL design and verification.

You will design and debug RTL, SystemVerilog/UVM testbenches, teach AI models how to interpret specifications, and help translate engineering pain points into automated AI workflows that improve design productivity.

Qualifications

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of experience in RTL design, functional verification, and/or architecture-level modeling.
• Proficiency with Verilog/SystemVerilog, UVM, and simulation tools.
• Experience designing and verifying complex subsystems or SoCs, preferably in production or research tapeouts.
• Familiarity with lint, CDC, formal, coverage analysis, and synthesis flows.
• Interest or experience in AI/ML, especially AI-assisted engineering tools, is a major plus.
• Strong collaboration skills and a passion for enabling the next generation of EDA workflows.

Responsibilities

• Collaborate with AI engineers to model and codify chip design and verification workflows.
• Design, implement, and debug RTL designs and SystemVerilog/UVM testbenches used in training and validating AI agents.
• Provide deep domain expertise to help AI agents interpret specifications, generate RTL code, and understand verification coverage.
• Build reusable examples, design patterns, and edge cases to train and evaluate generative and agentic AI models.
• Support benchmarking and evaluation of AI-assisted design and verification productivity across realistic chip development tasks.
• Work closely with customers, product, and research teams to translate engineering pain points into automated AI workflows.

Skills

RTL design

SystemVerilog

UVM

Verilog

Simulation tools

SoC design

AI/ML interest

Education

Bachelor's/Master's/PhD in Electrical/Computer Engineering or related

Tools

Synopsys VCS

Cadence Xcelium

Siemens Questa

Job description

ChipAgents in Santa Barbara, CA, is seeking a Senior Design and Verification Engineer to join our core product and research team. You will collaborate with AI engineers to build agentic AI systems for EDA and shape how engineers think about RTL design and verification.

You will design and debug RTL, SystemVerilog/UVM testbenches, teach AI models how to interpret specifications, and help translate engineering pain points into automated AI workflows that improve design productivity.