Senior EDA Architect: RTL/Logic Verif for Scalable AI Chips

Cadence; San Jose (CA); On-site; USD 210,000 - 390,000; Full time

Benefits offered by this job

Paid vacation and holidays

401(k) with employer match

Employee stock purchase plan

Medical/dental/vision options

Job summary

Cadence is seeking a Senior Engineer for its System Verification Group in California to advance Xcelium RTL/logic simulator. You will design and optimize the simulator to handle AI and hyperscale chip designs, lead junior engineers, and collaborate with a distributed team.

You will work on C/C++ implementations, timing verification, and SDC constraints, writing specifications and unit tests while pushing performance improvements and scalable algorithms for multi-billion-node graphs.

Qualifications

• MS in CS or EE with 12+ years or PhD with 10+ years of experience.
• 10+ years in EDA software development.
• Strong RTL/Logic Simulation, SDC constraints, and Timing Analysis experience.
• Proficient in C/C++ and SystemVerilog/Verilog.
• Experience in multi-threaded/concurrent programming.
• Ability to learn new technologies quickly.
• Prior RTL/logic simulation software development experience is a plus.

Responsibilities

• Enhance and support Xcelium RTL/logic simulator engine with new features.
• Improve Timing Constraints Verification within Xcelium.
• Design and optimize graph algorithms for SDC constraints on large graphs.
• Perform bottleneck analysis and optimize C/C++ performance.
• Lead junior engineers and collaborate with a global team.
• Contribute to technical discussions, code reviews, and process improvements.
• Write specifications and unit tests for code.

Skills

C/C++

RTL/Logic Simulation

SDC constraints

SystemVerilog/Verilog

Multi-threaded programming

Algorithm optimization

Leadership

Education

MS in Computer Science or Electrical Engineering / PhD

Job description

Cadence is seeking a Senior Engineer for its System Verification Group in California to advance Xcelium RTL/logic simulator. You will design and optimize the simulator to handle AI and hyperscale chip designs, lead junior engineers, and collaborate with a distributed team.

You will work on C/C++ implementations, timing verification, and SDC constraints, writing specifications and unit tests while pushing performance improvements and scalable algorithms for multi-billion-node graphs.