Senior RTL/Logic Simulator Architect (C/C++)

Cadence Design Systems; San Jose (CA); On-site; USD 161,000 - 299,000; Full time

Job summary

Cadence Design Systems in California is seeking a Senior Engineer for the Xcelium Software Development Team to advance RTL/logic simulation for future AI and hyperscale chip designs. The role is based in California with a distributed global team focused on high‑quality RTL/logic simulation.

Responsibilities include enhancing the Xcelium engine, optimizing performance in C/C++, implementing graph algorithms for SDC constraints, and writing specifications and unit tests.

Qualifications

• MS/PhD in Computer Science or Electrical Engineering with 5+ years of experience OR PhD with 5+ years experience
• 5+ years of experience in EDA software development
• Excellent programming skills in C/C++ and strong knowledge of RTL/logic simulation
• Experience with RTL/logic simulation software development is a plus

Responsibilities

• Enhance and support Xcelium RTL/logic simulator engine and add new features
• Design, tune, and implement graph algorithms for SDC constraints on large graphs
• Improve compilation speed and memory footprint in C/C++
• Write specifications and unit tests for code

Skills

RTL/Logic simulation

C/C++ programming

Multi-threaded programming

SystemVerilog/Verilog

SDC constraints

Graph algorithms

Education

MS/PhD in Computer Science or Electrical Engineering

Job description

Cadence Design Systems in California is seeking a Senior Engineer for the Xcelium Software Development Team to advance RTL/logic simulation for future AI and hyperscale chip designs. The role is based in California with a distributed global team focused on high‑quality RTL/logic simulation.

Responsibilities include enhancing the Xcelium engine, optimizing performance in C/C++, implementing graph algorithms for SDC constraints, and writing specifications and unit tests.