Senior Principal Software Engineer

Cadence Design Systems; San Jose (CA); On-site; USD 161,000 - 299,000; Full time

Job summary

Cadence Design Systems in California is seeking a Senior Engineer for the Xcelium Software Development Team to advance RTL/logic simulation for future AI and hyperscale chip designs. The role is based in California with a distributed global team focused on high‑quality RTL/logic simulation.

Responsibilities include enhancing the Xcelium engine, optimizing performance in C/C++, implementing graph algorithms for SDC constraints, and writing specifications and unit tests.

Qualifications

• MS/PhD in Computer Science or Electrical Engineering with 5+ years of experience OR PhD with 5+ years experience
• 5+ years of experience in EDA software development
• Excellent programming skills in C/C++ and strong knowledge of RTL/logic simulation
• Experience with RTL/logic simulation software development is a plus

Responsibilities

• Enhance and support Xcelium RTL/logic simulator engine and add new features
• Design, tune, and implement graph algorithms for SDC constraints on large graphs
• Improve compilation speed and memory footprint in C/C++
• Write specifications and unit tests for code

Skills

RTL/Logic simulation

C/C++ programming

Multi-threaded programming

SystemVerilog/Verilog

SDC constraints

Graph algorithms

Education

MS/PhD in Computer Science or Electrical Engineering

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Join the team behind Xcelium, the industry-leading logic simulator, to architect the next generation of hardware verification technology. As a Senior Engineer in the System Verification Group, you will be at the forefront of EDA innovation, evolving the Xcelium simulator to meet the staggering complexity of future AI and hyperscale chip designs. You will be part of an innovative, geographically distributed team dedicated to advancing the capabilities of RTL/logic simulation for semiconductor technology. The work environment encourages collaboration, technical excellence, and continuous learning. We are looking for an experienced C/C++ software engineer to join the Xcelium Software Development Team to develop and enhance RTL/logic simulation products.

Responsibilities

Enhance and support Xcelium RTL/logic simulator engine to add new features and extend existing features. Enhance and support Timing Constraints Verification technology used inside Xcelium simulator. The role involves designing, tuning, and innovating graph algorithms involving SDC constraints support on multi‑billion‑node graphs. Conduct deep‑dive bottleneck analysis and implement performance optimizations in C/C++ to improve compilation speed and memory footprint. Collaborate with global team members to deliver high‑quality results in a distributed environment. Write Specifications and Unit Tests for your code.

Position Requirements / Qualifications

MS/PhD in Computer Science or Electrical Engineering. MS in Computer Science or Electrical Engineering with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience 5+ years of experience in EDA software development. Strong background in RTL/Logic Simulation, SDC constraints and Timing Analysis especially path exceptions handling in a STA tool. Excellent programming skills in C/C++ and a deep understanding of SystemVerilog or Verilog. Experience in multi-threaded/ concurrent programming. Ability to quickly learn new technologies and adapt to project requirements. Prior experience with RTL/logic simulation software development is an added plus.

Salary

The annual salary range for California is $161,000 to $299,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.

Benefits

• paid vacation and paid holidays
• 401(k) plan with employer match
• employee stock purchase plan
• a variety of medical, dental and vision plan options

Equal Employment Opportunity Policy

Cadence is committed to equal employment opportunity throughout all levels of the organization. Read the policy(opens in a new tab) We welcome your interest in the company and want to make sure our job site is accessible to all.

E-Verify

E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.