Senior Principal Software Engineer, RTL/Logic Simulation

Cadence Design Systems, Inc.; San Jose (CA); On-site; USD 161,000 - 299,000; Full time

Benefits offered by this job

Paid vacation

401(k) plan with employer match

Employee stock purchase plan

Health, dental and vision insurance

Job summary

Cadence Design Systems, Inc. seeks a Senior Engineer for the Xcelium Software Development Team in San Jose. You will contribute to RTL/logic simulation, enhance timing verification, and optimize graph algorithms handling SDC constraints on massive graphs.

Collaboration across global teams and rigorous testing are key parts of the role. The position emphasizes C/C++ engineering, SystemVerilog/Verilog expertise, and the ability to learn new technologies to support scalable silicon verification

Qualifications

• MS/PhD in Computer Science or Electrical Engineering required.
• 7+ years in EDA software development or 5+ years with a PhD.
• 5+ years of experience in EDA software development.

Responsibilities

• Enhance and support Xcelium RTL/logic simulator engine to add new features and extend existing features.
• Enhance and support Timing Constraints Verification technology used inside Xcelium simulator.
• Design, tune, and innovate graph algorithms involving SDC constraints on multi-billion-node graphs.
• Conduct deep-dive bottleneck analysis and implement performance optimizations in C/C++ to improve compilation speed and memory footprint.
• Collaborate with global team members to deliver high-quality results in a distributed environment.
• Write Specifications and Unit Tests for your code.

Skills

RTL/Logic Simulation

C/C++ programming

SystemVerilog/Verilog

Multi-threaded programming

SDC constraints

Performance optimization

Education

MS in Computer Science or Electrical Engineering

PhD in Computer Science or Electrical Engineering

Job description

Cadence Design Systems, Inc. seeks a Senior Engineer for the Xcelium Software Development Team in San Jose. You will contribute to RTL/logic simulation, enhance timing verification, and optimize graph algorithms handling SDC constraints on massive graphs.

Collaboration across global teams and rigorous testing are key parts of the role. The position emphasizes C/C++ engineering, SystemVerilog/Verilog expertise, and the ability to learn new technologies to support scalable silicon verification