Senior RTL/Logic Simulation Architect

Cadence Design Systems; San Jose (CA); On-site; USD 210,000 - 390,000; Full time

Benefits offered by this job

Paid vacation and paid holidays

401(k) with employer match

Employee stock purchase plan

Job summary

Cadence Design Systems in California is seeking a Senior Engineer for the System Verification Group to advance the Xcelium RTL/logic simulator and tackle the growing complexity of AI and hyperscale chip designs.

You will join a geographically distributed team, lead junior engineers, and contribute to timing analysis and graph algorithms; strong C++ and SystemVerilog skills are essential, with deep expertise in RTL/logic simulation.

Qualifications

• MS in Computer Science or Electrical Engineering with a minimum of 12 years of experience OR PhD with a minimum of 10 years of experience.
• 10+ years of experience in EDA software development, RTL/Logic Simulation, and SDC constraints.
• Excellent programming skills in C/C++ and a deep understanding of SystemVerilog or Verilog; experience with multi-threaded programming.

Responsibilities

• Enhance and support Xcelium RTL/logic simulator engine to add new features and extend existing features.
• Design, tuning, and innovation of graph algorithms involving SDC constraints on multi‑billion‑node graphs.
• Conduct deep-dive bottleneck analysis and implement performance optimizations in C/C++ to improve compilation speed and memory footprint.
• Lead junior engineers and collaborate with global team members to deliver high-quality results in a distributed environment.
• Write Specifications and Unit Tests for your code.

Skills

C++

SystemVerilog/Verilog

Multithreaded programming

Performance optimization

Leadership

Education

MS in Computer Science or Electrical Engineering

PhD with 10+ years

Job description

Cadence Design Systems in California is seeking a Senior Engineer for the System Verification Group to advance the Xcelium RTL/logic simulator and tackle the growing complexity of AI and hyperscale chip designs.

You will join a geographically distributed team, lead junior engineers, and contribute to timing analysis and graph algorithms; strong C++ and SystemVerilog skills are essential, with deep expertise in RTL/logic simulation.