Senior RTL-to-GDS Physical Design Engineer (3nm FinFET)

LanceSoft, Inc.; Folsom (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

LanceSoft, Inc. is seeking an experienced ASIC Physical Design engineer to own end-to-end RTL-to-GDS flows, with strong hands-on experience in GDSII/STA, clock tree synthesis (CTS), timing closure and signoff, and robust RTL block implementations.

Preference for candidates with 3nm FinFET exposure, advanced-node semiconductor projects, and backgrounds from Broadcom, Google, or Intel. The role is contract-based with an extension possibility up to 1 year 3 months.

Qualifications

• Experience with end-to-end RTL-to-GDS flows and robust GDSII/STA expertise.
• Strong knowledge of clock tree synthesis, CTS, timing closure and signoff.
• Hands-on ASIC physical design and implementation experience.
• Exposure to 3nm FinFET nodes preferred for advanced projects.

Responsibilities

• Day-to-day work will focus on RTL blocks, clock tree, timing and signoff activities.
• Contribute to end-to-end physical design flows and ensure design for manufacturability.
• Collaborate cross-functionally on timing closure and signoff milestones.

Skills

RTL-to-GDS flow

GDSII/STA

CTS/Clock Tree

Timing Closure

Signoff

ASIC Physical Design

Tools

Synopsys Compiler

Job description

LanceSoft, Inc. is seeking an experienced ASIC Physical Design engineer to own end-to-end RTL-to-GDS flows, with strong hands-on experience in GDSII/STA, clock tree synthesis (CTS), timing closure and signoff, and robust RTL block implementations.

Preference for candidates with 3nm FinFET exposure, advanced-node semiconductor projects, and backgrounds from Broadcom, Google, or Intel. The role is contract-based with an extension possibility up to 1 year 3 months.