Physical Design Engineer (RTL-to-GDSII)

TekClap; San Jose (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

TekClap in San Jose, CA is seeking highly skilled Physical Design Engineers with hands-on RTL-to-GDSII implementation experience for advanced-node ASIC/SoC designs.

Responsibilities include RTL-to-GDSII flow, CTS, routing, and timing closure, along with physical verification and ECO-driven optimization to meet PPA targets. You will collaborate with cross-functional teams to ensure successful tapeouts.

Qualifications

• RTL-to-GDSII implementation, including synthesis, floorplanning, placement, CTS, routing, and timing closure.
• Physical verification and signoff activities.
• ECO implementation and design optimization to meet PPA targets.
• Collaboration with cross-functional teams to ensure successful tapeout delivery.

Responsibilities

• RTL-to-GDSII implementation, including synthesis, floorplanning, placement, CTS, routing, and timing closure.
• Physical verification and signoff activities.
• ECO implementation and design optimization to meet PPA targets.
• Collaboration with cross-functional teams to ensure successful tapeout delivery.

Skills

Clock Tree Synthesis

Static Timing Analysis

RTL-to-GDSII implementation

Physical verification

Tapeout signoff

Tools

PrimeTime

StarRC Extraction

RedHawk-SC EMIR Analysis

Formality ECO and Prime Closure

Job description

We are seeking highly skilled Physical Design Engineers with hands-on experience across the complete RTL-to-GDSII implementation flow for advanced-node ASIC/SoC designs.

Key Responsibilities

• RTL-to-GDSII implementation, including synthesis, floorplanning, placement, CTS, routing, and timing closure


• Physical verification and signoff activities


• ECO implementation and design optimization to meet PPA targets


• Collaboration with cross-functional teams to ensure successful tapeout delivery

Required Expertise

• Clock Tree Synthesis (CTS)


• Static Timing Analysis using PrimeTime


• StarRC Extraction


• RedHawk-SC EMIR Analysis


• Formality ECO and Prime Closure

Preferred Qualifications

• Experience with 5nm/3nm technology nodes


• Full-chip or block-level signoff and tapeout experience