Senior ASIC Physical Design Engineer – RTL2GDS, High-PPA

Google LLC; Mountain View (CA); On-site; USD 163,000 - 236,000; Full time

Job summary

Google is seeking a Senior Physical Design Engineer in Mountain View to drive RTL2GDS implementation for high power, performance, and area designs. You will own physical design flows from synthesis to sign-off and collaborate with hardware, software, and EDA teams to deliver packed silicon.

The role emphasizes strong expertise in Verilog/SystemVerilog, scripting (Tcl/Perl), and advanced PPA optimizations. In-person interviews are typical, and competitive compensation includes equity and benefits.

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 8 years of physical design experience.
• Experience with synthesis and PnR tools (Genus, Innovus, DC, ICC).
• STA and sign-off optimization experience.

Responsibilities

• Develop RTL2GDS for high Power, Performance, and Area (PPA) designs.
• Define and implement schemes to improve performance and power.
• Collaborate with cross-functional teams to deliver quality results.

Skills

Tcl scripting

Verilog/SystemVerilog

Circuit design fundamentals

Education

Bachelor's degree in Electrical Engineering

Tools

Genus

Innovus

DC

ICC

Job description

Google is seeking a Senior Physical Design Engineer in Mountain View to drive RTL2GDS implementation for high power, performance, and area designs. You will own physical design flows from synthesis to sign-off and collaborate with hardware, software, and EDA teams to deliver packed silicon.

The role emphasizes strong expertise in Verilog/SystemVerilog, scripting (Tcl/Perl), and advanced PPA optimizations. In-person interviews are typical, and competitive compensation includes equity and benefits.