Contract Physical Design Engineer

LanceSoft, Inc.; Folsom (CA); Vor Ort; USD 140.000 - 210.000; Vollzeit

Zusammenfassung

LanceSoft, Inc. is seeking an experienced ASIC Physical Design engineer to own end-to-end RTL-to-GDS flows, with strong hands-on experience in GDSII/STA, clock tree synthesis (CTS), timing closure and signoff, and robust RTL block implementations.

Preference for candidates with 3nm FinFET exposure, advanced-node semiconductor projects, and backgrounds from Broadcom, Google, or Intel. The role is contract-based with an extension possibility up to 1 year 3 months.

Qualifikationen

• Experience with end-to-end RTL-to-GDS flows and robust GDSII/STA expertise.
• Strong knowledge of clock tree synthesis, CTS, timing closure and signoff.
• Hands-on ASIC physical design and implementation experience.
• Exposure to 3nm FinFET nodes preferred for advanced projects.

Aufgaben

• Day-to-day work will focus on RTL blocks, clock tree, timing and signoff activities.
• Contribute to end-to-end physical design flows and ensure design for manufacturability.
• Collaborate cross-functionally on timing closure and signoff milestones.

Kenntnisse

RTL-to-GDS flow

GDSII/STA

CTS/Clock Tree

Timing Closure

Signoff

ASIC Physical Design

Tools

Synopsys Compiler

Jobbeschreibung

• Strong end-to-end RTL-to-GDS flow experience:
• APR (Automatic Place & Route) experience is a key requirement.
• 3nm FinFET process experience is highly preferred/important.
• Strong GDS/GDSII and STA (Static Timing Analysis) experience required.
• Strong experience with Clock Tree / CTS, Timing Closure, and Signoff.
• Synopsys Compiler tools are highly desirable.
• Day-to-day work will primarily involve RTL blocks, Clock Tree, Timing, and Signoff activities.
• Candidates should have strong hands-on ASIC Physical Design / Implementation experience.

Preferred Candidate Background:

• Candidates from Broadcom, Google, Intel, etc. are highly preferred.
• Preference for candidates with experience in advanced-node semiconductor projects, especially 3nm FinFET.

Duration:

• Potential extension: 1 additional year
• Expected total duration: up to 1 year 3 months, depending on project requirements.