ASIC Physical Design Engineer: RTL-to-GDS & Signoff Expert

Neetha Consulting LLC; Cupertino (CA); Hybrid; USD 125,000 - 145,000; Full time

Job summary

Neetha Consulting LLC is seeking a Physical Design Engineer in Cupertino, CA for a full-time role. The position involves leading RTL to GDS implementations through the ASIC flow, and managing floorplanning, placement, clock tree synthesis, routing, and signoff readiness.

The candidate will optimize high-performance, low-power designs at advanced nodes (TSMC N5/N4P/N3), perform timing closure, UPF, and power planning while driving automation via Python/Perl/TCL scripts.

Qualifications

• Master’s or foreign equivalent in Electrical Engineering, Computer Engineering, or related field.
• Must be able to travel/relocate to various client sites across the U.S.

Responsibilities

• Conceptualize, design, and productize advanced RTL to GDS implementations through ASIC design flow.
• Lead the physical design closure process including floorplanning, placement, clock tree synthesis, routing, and optimization.
• Develop efficient IC block layouts optimized for area, timing, and power at advanced technology nodes (e.g., TSMC N5/N4P/N3).
• Drive implementation of high-performance, low-power, manufacturable designs.
• Perform synthesis, pre-layout STA, SDC constraints development, bump placement, power planning, MV design techniques, and UPF.
• Apply timing closure techniques: clock skew balancing, delay optimization, OCV handling, and ECO management.
• Conduct power and area optimization using Multi-Vt, clock gating, and power-aware synthesis.
• Manage post-layout STA, functional/timing ECOs, and high-frequency IP designs closure.
• Ensure physical verification (DRC, LVS, PERC, ERC, Antenna, EMIR, Power signoff) compliance with foundry sign-off standards.
• Collaborate with cross-functional teams to resolve design and manufacturing issues.
• Drive scripting and automation (Python, Perl, TCL) to enhance design efficiency.
• Use EDA tools (Innovus, ICCII, Fusion Compiler, Tempus, PrimeTime) for implementation and signoff readiness.

Education

Master's degree in Electrical Engineering

Tools

Innovus

ICCII

Fusion Compiler

Tempus

PrimeTime

Job description

Neetha Consulting LLC is seeking a Physical Design Engineer in Cupertino, CA for a full-time role. The position involves leading RTL to GDS implementations through the ASIC flow, and managing floorplanning, placement, clock tree synthesis, routing, and signoff readiness.

The candidate will optimize high-performance, low-power designs at advanced nodes (TSMC N5/N4P/N3), perform timing closure, UPF, and power planning while driving automation via Python/Perl/TCL scripts.