Senior Design Engineer: SOCs, RTL & Timing Expert

Cadence; Cary (NC); On-site; USD 140,000 - 260,000; Full time

Job summary

Cadence in the United States is seeking an experienced hardware senior engineer to lead a team that designs SOCs and sub-system chips. You will oversee RTL synthesis, floor planning, clock trees, timing closure, IR drop, and physical verification, coordinating Front End RTL and Back End verification teams.

Required BS in Electrical Engineering with 7+ years (MS 5+ years or PhD 1+ year). Proficiency with Cadence tools (Innovus, Tempus, QRC, Voltus, Pegasus) and exposure to 5nm/3nm/2nm nodes,

Qualifications

• BS in Electrical Engineering with 7+ years experience, or MS with 5+ years, or PhD with 1+ year.
• Experience with Cadence tools such as Innovus, Tempus, QRC, Voltus and Pegasus.
• Experience with advanced technologies like 5nm, 3nm and 2nm nodes.
• Experience using Linux servers, scripting with Shell/Perl/TCL.
• Knowledge of PCIe, DDR, LPDDR, SRAM, UCIe interfaces.

Responsibilities

• Lead a team to implement SOCs or sub system chips.
• Work on RTL synthesis and floor planning.
• Build clock trees and perform optimizations.
• Close timing, IR drop and physical verification.
• Review and document designs for taping out.
• Interface with Front End RTL design teams and Back End verification teams.

Skills

Team leadership

RTL design coordination

Scripting skills

Education

BS in Electrical Engineering

MS in Electrical Engineering

PhD in Electrical Engineering

Tools

Innovus

Tempus

QRC

Voltus

Pegasus

Job description

Cadence in the United States is seeking an experienced hardware senior engineer to lead a team that designs SOCs and sub-system chips. You will oversee RTL synthesis, floor planning, clock trees, timing closure, IR drop, and physical verification, coordinating Front End RTL and Back End verification teams.

Required BS in Electrical Engineering with 7+ years (MS 5+ years or PhD 1+ year). Proficiency with Cadence tools (Innovus, Tempus, QRC, Voltus, Pegasus) and exposure to 5nm/3nm/2nm nodes,