SoC Design Lead — RTL, Timing & Verification

Cadence; San Jose (CA); On-site; USD 140,000 - 260,000; Full time

Job summary

Cadence in California is seeking an experienced hardware/SoC design leader to guide a team developing next‑generation subsystems. You will oversee RTL synthesis, floor planning, clock-tree optimization, and physical verification across Front End RTL and Back End teams.

The role requires strong expertise with Cadence tools (Innovus, Tempus, QRC, Voltus, Pegasus) and deep knowledge of 5nm/3nm/2nm processes, Linux scripting, and standard interfaces (PCIe, DDR, LPDDR, SRAM, UCIe).

Qualifications

• Experience with Cadence tools: Innovus, Tempus, QRC, Voltus and Pegasus.
• Experience with advanced technologies like 5nm, 3nm and 2nm nodes.
• Proficiency with Linux servers; scripting with Shell/Perl/TCL.
• Knowledge of PCI Express, DDR, LPDDR, SRAM, UCIe interfaces.

Responsibilities

• Lead a team to implement SOCs or subsystem chips.
• Work on RTL synthesis and floor planning.
• Build clock trees and perform optimizations.
• Close timing, IR drop and physical verification.
• Review and document designs for taping out.
• Interface with Front End RTL design teams and Back End verification teams.

Skills

SOC design leadership

RTL synthesis

Floor planning

Timing closure

Physical verification

Team coordination

Education

BS in Electrical Engineering (minimum 7 years)

MS in Electrical Engineering (minimum 5 years)

PhD in Electrical Engineering (minimum 1 year)

Tools

Cadence Innovus

Cadence Tempus

Cadence QRC

Cadence Voltus

Cadence Pegasus

Job description

Cadence in California is seeking an experienced hardware/SoC design leader to guide a team developing next‑generation subsystems. You will oversee RTL synthesis, floor planning, clock-tree optimization, and physical verification across Front End RTL and Back End teams.

The role requires strong expertise with Cadence tools (Innovus, Tempus, QRC, Voltus, Pegasus) and deep knowledge of 5nm/3nm/2nm processes, Linux scripting, and standard interfaces (PCIe, DDR, LPDDR, SRAM, UCIe).