Senior RTL Engineer - High-Speed IO & Chiplet Architect

Energy Jobline ZR; San Jose (CA); Presencial; USD 138.000 - 206.000; Jornada completa

Descripción de la vacante

Samsung Semiconductor is seeking an experienced RTL engineer to develop and integrate IO die RTL (Verilog/SystemVerilog) and high-speed interconnect IP, including PCIe, UCIe, and CXL, for a multi-die, chiplet-based platform.

You will own microarchitecture and RTL for IO subsystems, collaborate with verification and architecture teams, and drive automation of IP integration workflows while delivering on time and within power/area targets.

Formación

• Bachelor’s degree with 5+ years, or Master’s with 3+ years, or PhD with 0+ years of industry experience.
• Strong background in microarchitecture and RTL design for complex SoC and die integration.
• 5+ years of RTL development experience for high-speed interconnect/IO subsystems.
• Hands‑on experience integrating interconnect IP such as PCIe, CXL, UCIe, and die‑to‑die interfaces.
• Experience modifying third‑party interconnect IP to meet die‑level requirements.
• Familiarity with chiplet-based multi‑die architectures and die‑to‑die interconnect.
• Proficiency in scripting (Tcl, Python, or Perl) for design integration.

Responsabilidades

• Develop RTL (Verilog/SystemVerilog) for the IO die and integrate PCIe, UCIe, and other high-speed interconnect IP.
• Define and implement die-to-die and chiplet interfaces using UCIe with protocol compliance.
• Own the microarchitecture and RTL for IO subsystems such as PCIe/CXL controllers and interconnect fabric bridges.
• Collaborate with verification to develop test plans and debug issues at IP and die levels.
• Work with architecture, PHY/SerDes, physical design, and software to meet performance/power/area targets.
• Automate IP integration and RTL assembly flows using scripting and AI tools.
• Communicate with stakeholders to ensure timely, on-budget die delivery.

Conocimientos

RTL development (Verilog/SystemVerilog

SoC/die integration

Interconnect IP integration (PCIe/CXL/

UCIe knowledge

Chiplet architecture

Scripting (Tcl/Python/Perl)

IP customization & integration

Analytical problem solving

Communication & collaboration

AI/ML workload awareness

Educación

Bachelor’s degree in EE/related field

Master’s degree

PhD

Herramientas

IP-XACT

Python

Verilog/SystemVerilog tooling

Descripción del empleo

Samsung Semiconductor is seeking an experienced RTL engineer to develop and integrate IO die RTL (Verilog/SystemVerilog) and high-speed interconnect IP, including PCIe, UCIe, and CXL, for a multi-die, chiplet-based platform.

You will own microarchitecture and RTL for IO subsystems, collaborate with verification and architecture teams, and drive automation of IP integration workflows while delivering on time and within power/area targets.