Senior High-Speed I/O Digital Design Engineer

Samsung Semiconductor

San Jose (CA)

On-site

USD 138,000 - 206,000

Full time

14 days+

A complete application in a minute

Tailored resume and cover letter, ready to send.

Get past ATS filters

Benefits offered by this job

PTO & holidays
Health and wellness programs
Competitive benefits

Job summary

Samsung Semiconductor’s San Jose location is seeking a senior Electrical Engineer to contribute to High-Speed I/O design for next-generation AI platforms. You will work on die-to-die interfaces, IP development, and verification while collaborating with system and analog teams to ensure robust performance.

Ideal candidates hold a BS in Electrical Engineering with 5+ years, or an MS/PhD with relevant experience, and have hands-on HSIO PHY IP experience plus strong SI/PI knowledge.

Qualifications

  • BS in Electrical Engineering with 5+ years of experience, MS in Electrical Engineering with 3+ years of experience or PhD in Electrical Engineering.
  • Hands-on experience in High-Speed I/O PHY IP development.
  • Strong understanding of high-speed serial interconnect protocols and design trade-offs.
  • Knowledge of Signal Integrity (SI) and Power Integrity (PI) modeling for High-Speed I/O designs.

Responsibilities

  • Develop and deliver HSIO PHY IP blocks for die-to-die interfaces.
  • Contribute to end-to-end digital design flows and verification.
  • Collaborate with system and analog teams to optimize performance.
  • Support design reviews and integrate IP into SoC projects.

Skills

High-Speed I/O
Digital design
SI/PI modeling
SoC protocols (AXI/CHi/PCIE)
End-to-end design flow

Education

BS EE
MS EE
PhD EE

Job description

Samsung Semiconductor’s San Jose location is seeking a senior Electrical Engineer to contribute to High-Speed I/O design for next-generation AI platforms. You will work on die-to-die interfaces, IP development, and verification while collaborating with system and analog teams to ensure robust performance.

Ideal candidates hold a BS in Electrical Engineering with 5+ years, or an MS/PhD with relevant experience, and have hands-on HSIO PHY IP experience plus strong SI/PI knowledge.

Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

Staff High-Speed I/O Digital & Mixed-Signal Engineer
Staff High-Speed I/O Digital & Mixed-Signal Engineer

Samsung-Semiconductor • San Jose (CA)

On-site
USD 163,000 - 253,000
Paid time off
Health benefits
Onsite gym
Senior HSIO Digital Design Engineer
Senior HSIO Digital Design Engineer

Samsung Semiconductor • San Jose (CA)

On-site
USD 138,000 - 206,000
PTO & holidays
Health and wellness programs
Competitive benefits
Staff HSIO Digital & Mixed Signal Design Engineer
Staff HSIO Digital & Mixed Signal Design Engineer

Samsung-Semiconductor • San Jose (CA)

On-site
USD 163,000 - 253,000
Paid time off
Health benefits
Onsite gym
Senior RTL Engineer - IO Die & Chiplet Interconnect
Senior RTL Engineer - IO Die & Chiplet Interconnect

Samsung Semiconductor • San Jose (CA)

On-site
USD 138,000 - 206,000
4+ weeks PTO
Onsite café and gym
Flexible work environment
+2
Senior RTL Engineer - High-Speed IO & Chiplet Architect
Senior RTL Engineer - High-Speed IO & Chiplet Architect

Energy Jobline ZR • San Jose (CA)

On-site
USD 138,000 - 206,000
Senior High-Speed PHY & IO Design Engineer
Senior High-Speed PHY & IO Design Engineer

Sandisk • Milpitas (CA)

On-site
USD 140,000 - 210,000
Senior High-Speed Digital Engineer (Automotive Systems)
Senior High-Speed Digital Engineer (Automotive Systems)

Tensor Auto • San Jose (CA)

On-site
USD 240,000 - 400,000
Staff Serdes Analog Design Engineer — High-Speed IP
Staff Serdes Analog Design Engineer — High-Speed IP

Samsung-Semiconductor • San Jose (CA)

On-site
USD 163,000 - 253,000
Paid time off
Fertility support
Medical travel support
+1
Staff Engineer, Serdes Analog Design – High‑Speed Interconnects
Staff Engineer, Serdes Analog Design – High‑Speed Interconnects

Samsung Semiconductor Inc. • San Jose (CA)

On-site
USD 157,000 - 243,000
Medical/Dental/Vision/401k
4+ weeks PTO annually
Fertility care stipend
+2
High-Speed IO Validation Engineer for PCIe/Gen5+ Systems
High-Speed IO Validation Engineer for PCIe/Gen5+ Systems

Advanced Micro Devices, Inc. • Santa Clara (CA)

On-site
USD 120,000 - 180,000