Senior RTL IP Engineer - Memory-Centric AI/ML

Samsung Semiconductor; San Jose (CA); On-site; USD 138,000 - 206,000; Full time

Benefits offered by this job

4+ weeks PTO

Onsite Café & gym

Fertility care stipend

Medical travel support

Virtual pet care

Confidential therapy sessions

Flexible work policy

Job summary

Samsung Semiconductor in San Jose, CA seeks an experienced hardware design engineer to develop memory-centric IP using Verilog, SystemVerilog and HLS, focusing on performance, power, and area.

You will collaborate with verification and design teams, requiring 5+ years in RTL design for complex IPs and expertise in memory controller IP and AI/ML workloads. Competitive pay and onsite facilities provided.

Qualifications

• Bachelor’s degree in Electrical Engineering or related field with 5+ years experience.
• Master’s degree in Electrical Engineering or related field with 3+ years experience preferred.
• PhD with relevant research is acceptable for senior roles.

Responsibilities

• Develop IP for memory-centric computing systems using Verilog, SystemVerilog and HLS.
• Optimize IP for performance, power, and area with advanced design techniques.
• Collaborate with verification engineers to design and develop test plans.
• Make design decisions across performance, power, thermal, and cost.
• Troubleshoot hardware issues and ensure design quality through verification.
• Stay up-to-date with AI/ML workloads and related hardware trends.
• Communicate with stakeholders to deliver projects on time and within budget.

Skills

Microarchitecture

Computer Architecture

RTL development

Memory Controller IP

AI/ML workloads

Analytical skills

Communication skills

Team collaboration

Education

Bachelor’s degree in Electrical Engineering or related field

Master’s degree in Electrical Engineering or related field

PhD (optional/research)

Job description

Samsung Semiconductor in San Jose, CA seeks an experienced hardware design engineer to develop memory-centric IP using Verilog, SystemVerilog and HLS, focusing on performance, power, and area.

You will collaborate with verification and design teams, requiring 5+ years in RTL design for complex IPs and expertise in memory controller IP and AI/ML workloads. Competitive pay and onsite facilities provided.