Senior RTL Engineer - IO Die & Chiplet Interconnect

Samsung Semiconductor; San Jose (CA); On-site; USD 138,000 - 206,000; Full time

Benefits offered by this job

4+ weeks PTO

Onsite café and gym

Flexible work environment

Fertility/adoption support

Employee charitable giving match

Job summary

Samsung Semiconductor in San Jose, CA is seeking an experienced RTL/SoC design engineer to develop and integrate high-speed interconnect IP for a chiplet-based IO die. You will own microarchitecture, work with verification, architecture, PHY/SerDes, and software teams to meet performance and power goals.

Candidates should have 5+ years of RTL development, strong interconnect experience (PCIe/CXL/UCIe), and scripting skills; a collaborative, proactive mindset is essential.

Qualifications

• Extensive RTL development experience for high-speed interconnect and IO subsystems.
• Hands-on experience integrating PCIe, CXL, UCIe IP and die-to-die interfaces.
• Familiarity with chiplet-based multi-die architectures and IP packaging.
• Proficiency in scripting for design automation; experience with agentic AI tools is a plus.

Responsibilities

• Develop RTL (Verilog/SystemVerilog) for the IO die and integrate PCIe/CXL/UCIe IP.
• Define and implement die-to-die interfaces using UCIe across chiplets.
• Own microarchitecture and RTL for IO subsystems including controllers and bridges.
• Collaborate with verification to plan tests and debug at IP/subsystem level.
• Automate IP integration flows using scripting to improve throughput.

Skills

RTL development

Interconnect IP integration

UCIe chiplet architectures

PCIe/CXL protocol stacks

Scripting (Tcl, Python, Perl)

SoC integration methods (IP-XACT)

Die-to-die interfaces

AI/ML workloads experience

Analytical problem solving

Communication & collaboration

Education

Bachelor’s degree in Electrical/Computer Engineering

Master’s degree in Electrical/Computer Engineering

PhD in related field

Job description

Samsung Semiconductor in San Jose, CA is seeking an experienced RTL/SoC design engineer to develop and integrate high-speed interconnect IP for a chiplet-based IO die. You will own microarchitecture, work with verification, architecture, PHY/SerDes, and software teams to meet performance and power goals.

Candidates should have 5+ years of RTL development, strong interconnect experience (PCIe/CXL/UCIe), and scripting skills; a collaborative, proactive mindset is essential.