Lead, Physical Design & STA for FPGA SoCs

191 Altera Corporation; San Jose (CA); On-site; USD 149,100 - 215,000; Full time

Job summary

Altera seeks an experienced Physical Design Implementation & STA Lead to drive high-quality physical implementation and timing closure for next-generation FPGA SoCs. You will lead block-level implementation, CTS, ECOs, and signoff activities, coordinating with RTL, CAD, DFT, and library teams.

This senior role involves project leadership and mentoring, with emphasis on ML/AI-assisted design methodologies, timing constraints, and robust signoff processes.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field with 7+ years in physical design or STA.
• 7+ years in physical design/SoC backend development for advanced semiconductor products.
• 3+ years of experience performing static timing analysis using Synopsys PrimeTime or equivalent STA tools (MMMC timing).

Responsibilities

• Lead block-level physical implementation including synthesis, floorplanning, place-and-route, CTS, optimization, and ECO closure.
• Support SoC-level physical implementation and collaborate on floorplanning, partitioning, and integration strategies.
• Develop and maintain implementation constraints (SDC and UPF) to meet timing, power, and area goals.
• Partner with RTL, DFT, CAD, packaging, and library teams to resolve implementation issues throughout the design cycle.
• Drive implementation convergence across timing, power, congestion, and routability objectives.
• Execute signoff activities including IR drop, electromigration, DRC, LVS, antenna, and physical verification.

Skills

Physical design

Implementation

Static timing analysis

Synthesis

Floorplanning

Place-and-route

CTS

ECO closure

Python automation

Education

Bachelor’s degree in Electrical Engineering or related

Tools

Synopsys PrimeTime

UPF

Synthesis tools

Job description

Altera seeks an experienced Physical Design Implementation & STA Lead to drive high-quality physical implementation and timing closure for next-generation FPGA SoCs. You will lead block-level implementation, CTS, ECOs, and signoff activities, coordinating with RTL, CAD, DFT, and library teams.

This senior role involves project leadership and mentoring, with emphasis on ML/AI-assisted design methodologies, timing constraints, and robust signoff processes.