Senior Lead Design Engineer - RTL Design

Altera; San Jose (CA); Presencial; USD 232.000 - 330.000; Jornada completa

Descripción de la vacante

Altera is seeking a Senior Lead Design Engineer - RTL Design to provide hands-on technical leadership across RTL architecture, design, integration, and delivery for next-generation FPGA and programmable SoC solutions. This role combines technical leadership with individual contribution across global engineering teams.

You will drive design specifications, timing, verification alignment, and collaboration with verification, physical design, firmware, and software teams to ensure successful

Formación

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related technical discipline.
• Demonstrated hands-on RTL design leadership from architecture to post-silicon validation.
• Strong Verilog/SystemVerilog RTL development, synthesis, lint, and timing constraints.

Responsabilidades

• Lead RTL architecture and implementation for FPGA/SoC subsystems focusing on high-throughput datapaths.
• Own RTL blocks and subsystems, ensuring reusable, synthesizable, scalable, and testable code.

Conocimientos

Verilog/SystemVerilog

RTL design and implementation

Synthesis and lint

CDC/RDC and timing constraints

Architecture and microarchitecture

Board/firmware/software collaboration

Python/Tcl scripting

Leadership and mentorship

Educación

Bachelor’s degree in Electrical/Computer Engineering or related

Advanced degree preferred

Descripción del empleo

About The Role

Altera is seeking a Senior Lead Design Engineer - RTL Design to provide hands‑on technical leadership for the RTL architecture, design, integration, and delivery of next‑generation FPGA and programmable SoC solutions. This is a technical leadership, individual‑contributor role for an engineer who can set technical direction across complex subsystems, product generations, and global engineering teams.

Job Details

Job Description

About The Role

Altera is seeking a Senior Lead Design Engineer - RTL Design to provide hands‑on technical leadership for the RTL architecture, design, integration, and delivery of next‑generation FPGA and programmable SoC solutions. This is a technical leadership, individual‑contributor role for an engineer who can set technical direction across complex subsystems, product generations, and global engineering teams.

Responsibilities

• Lead RTL architecture, microarchitecture, and implementation for complex FPGA, programmable SoC, and infrastructure‑class subsystems, with emphasis on high‑throughput datapaths, memory access, interconnect, packet or data processing, and programmable acceleration.
• Own RTL design for critical blocks and subsystem integrations, ensuring code is reusable, synthesizable, scalable, testable, and aligned to performance, power, area, and timing objectives.
• Define design specifications, interface contracts, clocking and reset strategies, performance targets, and implementation plans that align architecture, verification, physical design, firmware, software, and product requirements.
• Drive technical tradeoffs across throughput, latency, bandwidth, buffering, power, area, timing, reliability, scalability, cost, and schedule; identify and mitigate architectural and execution risks early.
• Establish and advance RTL design methodologies, including coding standards, lint, CDC/RDC, synthesis, formal checks, automation, and design‑review practices that improve engineering quality and predictability.
• Partner with design verification to shape verification strategy, review test plans and coverage, triage failures, and drive efficient closure of complex pre‑silicon issues.
• Collaborate with physical design, CAD, DFT, emulation, FPGA prototyping, board, firmware, software, and post‑silicon teams to preserve RTL intent through implementation, timing closure, validation, and product delivery.
• Lead root‑cause analysis and resolution of complex design, integration, performance, and system‑level issues using disciplined debug and data‑driven decision‑making.
• Provide technical mentorship and RTL leadership across teams; raise the engineering bar through architecture reviews, RTL/code reviews, and constructive guidance to senior and developing engineers.
• Influence design roadmaps and collaborate with internal teams and external partners on reusable IP, EDA capabilities, and implementation approaches that strengthen Altera’s programmable technology portfolio.

What You Will Bring

You are a hands‑on RTL design leader who combines technical depth with broad systems perspective. You bring rigorous engineering judgment, a practical approach to execution, and a collaborative leadership style that enables teams to solve complex problems and deliver differentiated programmable solutions. You are motivated by building the foundational technology that allows Altera customers to create what is next.

Salary Range

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job‑related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$231,500 - $330,000 USD

We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.

Qualifications

Minimum Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline, with 15+ years of relevant experience in FPGA, ASIC, SoC, or semiconductor product development; advanced degree preferred.
• Demonstrated technical leadership delivering complex digital designs from architecture and microarchitecture through RTL, verification, integration, implementation, and post‑silicon or hardware validation.
• Deep hands‑on expertise in Verilog and/or SystemVerilog RTL development, synthesis, lint, CDC/RDC, formal or equivalence checking, timing constraints, and implementation‑aware design practices.
• Proven experience designing high‑performance digital subsystems, such as network or data‑processing pipelines, memory controllers or memory subsystems, on‑chip interconnect, traffic‑management logic, PCIe/CXL, Ethernet, high‑speed interfaces, or programmable acceleration engines.
• Strong understanding of architectural and RTL‑level tradeoffs involving bandwidth, latency, congestion, buffering, throughput, power, area, timing, and reliability.
• Experience leading design execution across multiple functional blocks or complex subsystem integration, including technical planning, risk management, schedule alignment, and prioritization.
• Demonstrated ability to collaborate and influence across architecture, design verification, physical design, DFT, CAD, firmware/software, system validation, and product engineering organizations.
• Strong written and verbal communication skills, with the ability to clearly communicate design intent, technical risks, and recommended solutions to diverse audiences.

Preferred Qualifications

• Experience designing RTL for FPGA architectures, programmable‑logic devices, configurable interconnect, SmartNICs, IPUs, SoCs, or data‑center acceleration platforms.
• Experience building, maintaining, or deploying reusable RTL IP across multiple products, technology nodes, or programs.
• Experience with high‑bandwidth memory architectures, packet buffering, lookup or classification engines, flow control, or high‑speed connectivity subsystems.
• Experience with FPGA prototyping, emulation, silicon bring‑up, post‑silicon debug, or performance optimization.
• Proficiency in scripting and workflow automation using Python, Tcl, Perl, or shell.
• A record of technical leadership through patents, publications, standards contributions, or sustained methodology innovation.

Job Type

Regular

Shift

Shift 1 (United States of America)

Primary Location

San Jose, California, United States

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.