Senior Design Verification Engineer – AI Accelerator

Acceler8 Talent; Palo Alto (CA); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Medical insurance

401(k)

Vision insurance

Dental insurance

Job summary

Acceler8 Talent seeks an experienced Design Verification Engineer in Palo Alto to own ASIC/SoC verification, testbench development, and coverage. You will work with RTL designers to identify issues, improve verification quality, and ensure silicon readiness for a next-generation AI accelerator.

The role is highly hands-on with ownership across verification closure, regression, and collaboration with architecture teams to tape out first-generation silicon.

Qualifications

• Substantial hands-on experience in ASIC or SoC design verification with ownership.
• Strong understanding of digital logic and Verilog/SystemVerilog.
• Experience developing verification plans and testbenches.
• Debugging skills to identify root causes and verify fixes.
• Experience with functional coverage, regression testing, and verification closure.
• Ability to collaborate with RTL designers, architects, and hardware engineers.

Responsibilities

• Develop and execute verification plans based on architectural specs.
• Identify boundary conditions, corner cases, and potential failure modes.
• Build and maintain verification environments, testbenches, stimulation, and checking.
• Trace complex failures through RTL and collaborate with design engineers to resolve root causes.
• Develop and execute directed and constrained-random tests.
• Analyze functional coverage and drive verification completeness.
• Improve regression workflows and verification infrastructure.
• Support block-, subsystem-, and system-level integration verification.
• Drive verification closure and communicate risks and coverage gaps.

Skills

ASIC/SoC verification

RTL debugging

Verilog/SystemVerilog

Constrained-random verification

Tools

SystemVerilog

UVM

SVA (SystemVerilog Assertions)

Job description

Acceler8 Talent seeks an experienced Design Verification Engineer in Palo Alto to own ASIC/SoC verification, testbench development, and coverage. You will work with RTL designers to identify issues, improve verification quality, and ensure silicon readiness for a next-generation AI accelerator.

The role is highly hands-on with ownership across verification closure, regression, and collaboration with architecture teams to tape out first-generation silicon.