ASIC Design Engineer (RTL)

CyberCoders, Inc.; Colorado Springs (CO); On-site; USD 280,000 - 580,000; Full time

Job summary

CyberCoders, Inc. is seeking an experienced ASIC Design Engineer to own RTL blocks for next‑generation high‑performance chips. This on-site role can be based in San Jose, CA or Colorado Springs, CO, with total compensation from $280k to $580k.

You will drive microarchitecture, write Verilog/SystemVerilog RTL, push timing closure, and collaborate with verification, firmware, software, emulation, and lab bring‑up teams to ship silicon.

Qualifications

• A strong track record in digital IC design on ASICs or complex SoCs.
• Deep, hands-on Verilog and SystemVerilog RTL experience.
• Strong microarchitecture skills and sound RTL design methods.
• Proven experience taking designs through timing closure.
• The persistence and analytical skill to solve hard problems.
• Comfort working in a fast-moving, highly technical team where you have real ownership.

Responsibilities

• Turn architecture specs into detailed microarchitecture and defend your choices in design reviews.
• Write clean, high-performance Verilog/SystemVerilog RTL for complex logic, including pipelined datapaths, clock domain crossings, multi-clock and multi-power-domain designs, and low-power techniques.
• Integrate third-party IP into your blocks and ensure it works smoothly with the rest of the chip.
• Push designs through timing closure and tune for power, performance and area.
• Debug: track down and fix hard design issues at every stage, from simulation and emulation through post-silicon.
• Lab work: take part in silicon bring-up and validation, and see your design come to life.
• Cross-team work: work day to day with verification, firmware, software, emulation and validation engineers across the full ASIC lifecycle.

Job description

Job title: ASIC Design Engineer, RTL (Senior/Staff/Principal)

Location: San Jose, CA or Colorado Springs, CO (on-site)

Salary: $280k-580k total comp

Help design the chips that move the world's AI data. Every AI model trained in a hyperscale data center depends on silicon that moves huge amounts of data between processors, memory and storage, with no room for delay. We design that silicon. We're looking for experienced RTL designers to own key blocks of our next generation of high-performance ASICs, from the first spec review through bring-up in the lab. You won't be one small part of a huge org. Your designs will ship in products running in some of the largest data centers on the planet.

What you’ll own

• Microarchitecture: Turn architecture specs into detailed microarchitecture and clear design documents, and defend your choices in design reviews.
• RTL design: Write clean, high-performance Verilog/SystemVerilog for complex logic. That includes pipelined datapaths, clock domain crossings, multi-clock and multi-power-domain designs, and low-power techniques.
• Integration: Bring third-party IP into your blocks and make sure it works smoothly with the rest of the chip.
• Meeting PPA targets: Push designs through timing closure and tune for power, performance and area.
• Debug: Track down and fix hard design issues at every stage, from simulation and emulation through post-silicon.
• Lab work: Take part in silicon bring-up and validation, and see your design come to life.
• Cross-team work: Work day to day with verification, firmware, software, emulation and validation engineers across the full ASIC lifecycle.

What you bring

• A strong track record in digital IC design on ASICs or complex SoCs
• Deep, hands-on Verilog and/or SystemVerilog RTL experience
• Strong microarchitecture skills and sound RTL design methods
• Proven experience taking designs through timing closure
• The persistence and analytical skill to solve hard problems
• Comfort working in a fast-moving, highly technical team where you have real ownership