RTL Design Engineer

Acceler8 Talent; California; Presencial; USD 170.000 - 230.000; Jornada completa

Descripción de la vacante

Acceler8 Talent is seeking an RTL Design Engineer in Palo Alto to help build a next-generation AI accelerator. You will own RTL across ASIC/SoC blocks, driving from architectural concepts through implementation, verification, and tapeout readiness.

The role demands hands-on design leadership, strong Verilog/SystemVerilog expertise, and close collaboration with verification and physical design teams to meet timing, power and area targets.

Formación

• Extensive digital hardware design experience with hands-on ASIC/SoC RTL ownership.
• Strong proficiency in Verilog and SystemVerilog.
• Proven ability to derive RTL from architectural specs and implement it.
• Deep microarchitecture knowledge: datapaths, state machines, control logic.
• Knowledge of PPA optimization and its impact on implementation.
• Experience debugging complex RTL and timing issues with teams.
• History collaborating with verification, architecture, and physical teams.
• Staff-to-Principal level judgment with hands-on RTL design focus.

Responsabilidades

• Translate architectures into detailed microarchitecture and synthesizable RTL.
• Design and optimize datapaths, control logic, and interfaces.
• Trade off throughput, latency, power, and timing in designs.
• Own RTL development, debugging, and integration for major blocks.
• Collaborate with verification to define functionality and debug issues.
• Coordinate with physical design to analyse synthesis and timing feedback.
• Drive design improvements based on timing, power, and area needs.
• Own blocks through integration, verification closure, and tapeout readiness.
• Document key design decisions, risks, and trade-offs.

Conocimientos

Verilog/SystemVerilog

RTL development

PPA optimization

RTL debugging

Cross-team collaboration

Hands-on design

Herramientas

Synthesis

Static Timing Analysis

Physical design feedback

Descripción del empleo

RTL Design Engineer

Level:Staff / Principal

Palo Alto, CA

About the Role

An early-stage, venture-backed AI semiconductor startup is seeking an experienced RTL Design Engineer to help develop a next-generation chip purpose-built for large language model (LLM) inference.

The company is developing a specialized AI accelerator alongside its supporting software stack, with a focus on delivering efficient, high-performance inference.

This is a hands-on engineering role offering significant ownership across digital design, microarchitecture, verification, and physical implementation. You'll play a key role in bringing the company's first generation of silicon from architectural concepts through implementation and tapeout.

Key Responsibilities

• Translate high-level architectural specifications into detailed block-level microarchitecture and synthesizable RTL.
• Design, implement, and optimize complex datapaths, control logic, and inter-block interfaces.
• Make architectural and implementation trade-offs involving throughput, latency, power, area, and timing.
• Own RTL development, debugging, and integration for significant portions of the ASIC/SoC design.
• Collaborate with verification engineers to define expected functionality, debug failures, and resolve complex corner cases.
• Work closely with physical design teams to analyze synthesis results, timing constraints, and implementation feedback.
• Drive design improvements based on timing, power, and area requirements.
• Take ownership of assigned design blocks through integration, verification closure, and tapeout readiness.
• Document key design decisions, implementation risks, and technical trade-offs.

Required Qualifications

• Extensive experience in digital hardware design, with significant hands-on ownership of ASIC or SoC RTL development.
• Strong proficiency in Verilog and/or SystemVerilog.
• Proven ability to develop complex RTL from architectural specifications through implementation.
• Deep understanding of digital microarchitecture, including datapaths, state machines, control logic, concurrency, and cycle-level behavior.
• Strong knowledge of power, performance, and area (PPA) optimization and how RTL design choices influence physical implementation.
• Experience debugging complex RTL issues and resolving functional or timing-related challenges.
• Demonstrated collaboration with verification, microarchitecture, and physical design teams.
• Staff-to-Principal-level technical judgment, combined with a willingness to remain highly hands-on in RTL design and debugging.

Preferred Qualifications

• Experience designing AI accelerators, inference ASICs, GPUs, or other high-performance compute silicon.
• Familiarity with LLM inference workloads and specialized compute architectures.
• Experience with synthesis, static timing analysis, and physical design feedback.
• Previous involvement in successful ASIC/SoC tapeouts.
• Background working on first-generation silicon or early-stage hardware development.
• Experience collaborating across architecture, design verification, and physical implementation.

Why Join?

• Opportunity to help develop a purpose-built LLM inference accelerator from the ground up.
• Significant ownership of RTL and microarchitecture for first-generation silicon.
• Work directly with a highly technical founding engineering team.
• Influence key architectural decisions, design methodologies, and implementation strategies.
• Hands-on engineering environment with broad technical exposure and minimal organizational layers.
• Opportunity to make a meaningful impact on the development of next-generation AI computing hardware.

Hiring Process

The interview process typically consists of two to three conversations, including technical discussions covering previous projects, RTL design experience, and engineering problem-solving.

Additional details about the team, architecture, and technology roadmap will be shared under NDA as the process progresses.