Senior Chip Architect – LLM Inference SoC

Acceler8 Talent; California; On-site; USD 180,000 - 340,000; Full time

Benefits offered by this job

Medical insurance

401(k)

Vision insurance

Dental insurance

Job summary

Acceler8 Talent is seeking a seasoned Chip Architect in Palo Alto to help design a next-generation ASIC for LLM inference. You will translate architectural concepts into microarchitecture and work with RTL, verification, and physical design teams to deliver high-performance silicon.

You will evaluate trade-offs among throughput, latency, power, and area, shape future chip generations, and guide first-generation silicon from architecture through tapeout.

Qualifications

• Experience in ASIC/SoC architecture with ownership of hardware decisions.
• Deep knowledge of digital hardware architecture and design challenges.
• Proven ability to translate architecture into microarchitecture.

Responsibilities

• Translate high-level inference system requirements into chip and block-level microarchitecture specs.
• Develop architectural decisions across compute, memory hierarchy, interconnects, and data movement.
• Evaluate trade-offs for throughput, latency, power, performance, and area (PPA).
• Collaborate with RTL engineers to implement architectural requirements efficiently.
• Work with verification and physical design to resolve constraints.
• Analyze performance bottlenecks and drive architectural improvements with data.
• Assess workloads and hardware utilization to optimize inference performance.
• Support first-generation silicon development from architecture to tapeout readiness.
• Identify architectural limitations and opportunities for improvement from implementation feedback.
• Help define technical direction and evolution of future-generation accelerators.

Skills

ASIC Architecture

Microarchitecture

RTL Collaboration

Hardware Trade-offs

Performance Analysis

Team Collaboration

Hands-on Architecture

Job description

Acceler8 Talent is seeking a seasoned Chip Architect in Palo Alto to help design a next-generation ASIC for LLM inference. You will translate architectural concepts into microarchitecture and work with RTL, verification, and physical design teams to deliver high-performance silicon.

You will evaluate trade-offs among throughput, latency, power, and area, shape future chip generations, and guide first-generation silicon from architecture through tapeout.