Principal RTL Design Engineer

SambaNova; Austin (TX); On-site; USD 180,000 - 255,000; Full time

Benefits offered by this job

Equity

Health insurance

HSA with employer contribution

Job summary

SambaNova is seeking a Principal RTL Design Engineer to own the microarchitecture and RTL for the next-generation Reconfigurable Dataflow Unit (RDU). This senior IC role requires delivering from spec through tape-out, balancing power, performance, and area while meeting aggressive frequency targets.

You will write and debug SystemVerilog RTL, own PPA, and collaborate with verification, architects, and software teams to drive performance improvements and design quality.

Qualifications

• BS in Electrical Engineering, Computer Engineering, or Computer Science.
• 7+ years of industry experience in ASIC RTL design.
• Mastery of synthesizable SystemVerilog and SVA to capture design intent.
• High-frequency design experience with datapath pipelining and timing targets.
• Strong foundation in computer architecture, digital logic, and memory structures.
• Experience delivering blocks from microarchitecture through tape-out on production ASIC.

Responsibilities

• Own the microarchitecture and RTL for a major RDU block from spec to tape-out.
• Write, integrate, and debug synthesizable SystemVerilog RTL for full chip implementation.
• Own PPA for your area, achieving aggressive frequency targets.
• Drive timing closure and design quality including lint, CDC, LEC, and STA.
• Partner with verification to define verification intent and coverage.
• Work with architects and software to prototype features improving performance.
• Drive AI, automation, and new EDA tool methodologies in the design flow.
• Set the technical bar in design reviews and mentor engineers.

Skills

SystemVerilog

SVA

RTL design

Synthesis

STA

Python

Microarchitecture

Digital design

Lint

CDC

LEC

PPA optimization

Education

B.S. in Electrical Engineering, Computer Engineering, or Computer Science

M.S. in Electrical Engineering, Computer Engineering, or Computer Science

Tools

AXI

PCIe

Ethernet

HBM

DDR

Job description

The era of pervasive AI has arrived. In this era, organizations will use generative AI to unlock hidden value in their data, accelerate processes, reduce costs, drive efficiency and innovation to fundamentally transform their businesses and operations at scale.

SambaNova Suite™ is the first full-stack, generative AI platform, from chip to model, optimized for enterprise and government organizations. Powered by the intelligent SN40L chip, the SambaNova Suite is a fully integrated platform, delivered on-premises or in the cloud, combined with state-of-the-art open-source models that can be easily and securely fine-tuned using customer data for greater accuracy. Once adapted with customer data, customers retain model ownership in perpetuity, so they can turn generative AI into one of their most valuable assets.

About the team

The RTL design team builds the compute datapath, on-chip network, and memory subsystems inside SambaNova's RDU AI accelerator. Their work spans microarchitecture through tape-out, including RTL implementation, PPA trade-offs, quality gates like lint, CDC, and LEC, and timing closure with physical design.

About the role

SambaNova is looking for a Principal RTL Design Engineer to own the microarchitecture and RTL for our next-generation Reconfigurable Dataflow Unit (RDU), the silicon behind our AI acceleration systems. This is a senior individual contributor role where you'll take a block from microarchitecture specification through RTL, quality closure, and tape-out, owning the power, performance, and area trade-offs along the way. Frequency targets are aggressive, so how you pipeline a datapath and where you spend area to buy timing are essential aspects of the role.

Responsibilities

• Own the microarchitecture and RTL for a major block or subsystem of the RDU, from specification through tape-out, including the specs you write for complex blocks in compute, memory, or on-chip network subsystems
• Write, integrate, and debug synthesizable SystemVerilog RTL through the full chip implementation and production lifecycle
• Own PPA for your area, hitting aggressive frequency targets through datapath pipelining, retiming, and microarchitectural restructuring
• Drive timing closure and design quality for your area: synthesis, STA, critical-path iteration, lint, CDC, LEC, and SystemVerilog Assertions capturing design intent
• Partner with design verification to define verification intent and coverage for your block, and support debug of functional and gate-level failures
• Work with architects and software teams to prototype and evaluate features that improve application-level performance
• Drive AI, automation, and new EDA tool methodologies into the design flow
• Set the technical bar in design reviews and mentor design engineers

Required Qualifications

• B.S. in Electrical Engineering, Computer Engineering, or Computer Science
• 7+ years of industry experience in ASIC RTL design
• Mastery of synthesizable SystemVerilog for high-speed, high-performance ASICs, including SVA to capture design intent
• High-frequency design experience, including datapath pipelining, retiming, critical-path restructuring, and other microarchitectural techniques for hitting aggressive frequency targets
• Deep foundation in computer architecture and digital logic design, including arbitration, flow control, clock domain crossing, and memory structures
• Ownership of a complex block or subsystem from microarchitecture specification through tape-out on at least one production ASIC
• Experience converging power, performance, and area against real physical constraints, including floorplan, congestion, and timing feedback from the physical design team
• Hands-on experience with synthesis and static timing analysis, and with lint, CDC, and LEC quality flows
• Demonstrated technical leadership without formal authority, including setting direction in design reviews, arbitrating microarchitecture decisions, and mentoring engineers
• Scripting in Python for design and flow automation

Preferred Qualifications

• M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science
• Depth in one RDU domain: compute and dataflow datapath, on-chip network and interconnect, or memory subsystem
• Industry-standard interconnects and protocols including AXI, PCIe, Ethernet, and HBM or DDR
• AI and ML workload acceleration techniques, and dataflow or reconfigurable architectures
• Formal property checking applied to design intent
• Advanced TSMC nodes and multi-die or chiplet design
• Performance modeling and analysis to support architectural trade-offs
• Fluency with Claude or other AI tools applied to RTL design and flow development

Base Salary Range: $180,000—$255,000 USD

EEO Policy

SambaNova Systems is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard basis of age (40 and over), color, disability, gender identity, genetic information, marital status, military or veteran status, national origin/ancestry, race, religion, creed, sex (including pregnancy, childbirth, breastfeeding), sexual orientation, and any other applicable status protected by federal, state, or local laws.

Benefits Summary for US-Based, Full-Time Employment Positions

SambaNova offers a competitive total rewards package, including the base salary, plus equity and benefits. We cover 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents and offer a Health Savings Account (HSA) with employer contribution. We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans in addition to Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care. Our library of well-being benefits available to you and your dependents includes a full subscription to Headspace, Gympass+ membership with access to physical gyms, One Medical membership, counseling services with an Employee Assistance Program, and much more.