Senior DV Architect for AI SoC RDU

SambaNova; San Jose (CA); On-site; USD 180,000 - 255,000; Full time

Benefits offered by this job

Health insurance

Dental plan

Vision plan

Equity

HSA with employer contribution

Headspace

One Medical

Job summary

SambaNova is seeking a Principal Design Verification Engineer to own verification for the next-generation RDU, the reconfigurable dataflow silicon behind our ML/AI systems. You will define test plans, testbench architecture, coverage models, and sign-off criteria while shaping reusable DV infrastructure and workflows.

You’ll collaborate with design, architecture, compiler, and runtime teams to verify chips against production ML workloads, mentor engineers, and advance verification methodologies

Qualifications

• BS or MS in EE, CS, or CE with 7+ years of ASIC design verification experience.
• Hands-on SystemVerilog and SVA with UVM/OVM/VMM; Python/C++ scripting.
• Full-cycle DV ownership from test plan to tape-out on complex ASICs.

Responsibilities

• Own verification end to end for a major RDU subsystem: test plan, testbench, coverage, and sign-off.
• Build a coverage model and drive closure ahead of tape-out.
• Develop testbench components, agents, checkers, and stimuli at multiple levels.
• Serve as the technical authority for verification decisions and debugging.
• Own regression health and triage to root cause.
• Verify functional and performance behavior; extend DV infrastructure and AI-assisted flows.
• Contribute to emulation/FPGA prototyping and support silicon bring-up.
• Set technical bar through DV reviews and mentor engineers.

Skills

SystemVerilog

SVA

Python

C/C++

ASIC verification

Testbench debugging

Technical leadership

Education

BS in E E / CS / CE

MS/PhD in EE/CS/CE

Tools

Verification IP

Emulation/FPGA prototyping

PCIe/Ethernet/HBM verification

Job description

SambaNova is seeking a Principal Design Verification Engineer to own verification for the next-generation RDU, the reconfigurable dataflow silicon behind our ML/AI systems. You will define test plans, testbench architecture, coverage models, and sign-off criteria while shaping reusable DV infrastructure and workflows.

You’ll collaborate with design, architecture, compiler, and runtime teams to verify chips against production ML workloads, mentor engineers, and advance verification methodologies