Senior RTL Design Architect - SoC Interconnect & AXI/CHI

SBT; San Francisco (CA); On-site; USD 170,000 - 260,000; Full time

Job summary

SBT is seeking an experienced RTL design engineer for a confidential semiconductor client in San Francisco. You will implement RTL using Verilog/SystemVerilog for complex digital blocks and SoC subsystems, focusing on high‑performance interconnect logic and AMBA interfaces within AXI/ACE/CHI frameworks.

The role requires 7+ years in RTL/digital design for ASIC/SoC, with Masters or PhD in EE/CE or related field. Strong emphasis on synthesis, timing, and cache-coherent architectures.

Qualifications

• 7+ years of RTL or digital design experience for ASIC or SoC development.
• Deep expertise with RTL design using Verilog/SystemVerilog and synthesis.
• Strong knowledge of AMBA protocols (AXI, ACE, CHI) and memory coherence.

Responsibilities

• Perform RTL implementation using Verilog/SystemVerilog for complex blocks and SoCs.
• Design AMBA-based interfaces and interconnect components (AXI, AHB, APB, ACE).
• Develop RTL for coherent interconnect and CHI-based subsystems with protocol state machines.
• Optimize RTL and micro-architecture for performance, power, area, and timing.

Skills

RTL design

Verilog/SystemVerilog

AMBA AXI/ACE/CHI

Cache coherency concepts

Education

Master’s degree in Electrical Engineering

Ph.D. in Electrical Engineering or related field

Job description

SBT is seeking an experienced RTL design engineer for a confidential semiconductor client in San Francisco. You will implement RTL using Verilog/SystemVerilog for complex digital blocks and SoC subsystems, focusing on high‑performance interconnect logic and AMBA interfaces within AXI/ACE/CHI frameworks.

The role requires 7+ years in RTL/digital design for ASIC/SoC, with Masters or PhD in EE/CE or related field. Strong emphasis on synthesis, timing, and cache-coherent architectures.