Senior RTL Design Engineer - AI Accelerator

SambaNova; Austin (TX); On-site; USD 120,000 - 184,000; Full time

Job summary

SambaNova RTL Design Engineers design components of the Reconfigurable Dataflow Unit (RDU) ASICs behind our AI acceleration systems. You'll own blocks within a larger subsystem, contributing sections of the microarchitecture specification and carrying your blocks through implementation and silicon bring-up.

You will work alongside principal engineers, architects, design verification, and physical design teams, taking on larger blocks as you deepen your architectural knowledge.

Qualifications

• B.S. in Electrical/Computer Engineering or CS.
• 5+ years of experience in ASIC RTL design.
• Strong foundation in computer architecture and digital logic design.
• Proficient in SystemVerilog RTL design for high-speed ASICs.
• Ability to trade off power, performance, and area.
• Knowledge of AXI, PCIe, Ethernet, and HBM or DDR interconnects.
• Experience with RTL synthesis tools and static timing analysis.
• Proficiency with linting, CDC, and logical equivalence checking.
• Experience implementing SystemVerilog Assertions to check design intent.
• Familiarity with hardware performance analysis tools and simulators.
• Familiarity with Git for release management.
• Scripting: Python and Linux shell.

Responsibilities

• Own RTL blocks within a subsystem and contribute to microarchitecture specs.
• Write and debug SystemVerilog RTL for RDU ASICs.
• Carry blocks through implementation, tape-out, and silicon bring-up.
• Collaborate with design, verification, and physical design teams to build depth in architecture.

Skills

SystemVerilog

ASIC RTL design

Power/Performance/Area trade-offs

Digital logic

Python

Linux shell

Education

B.S. in Electrical Engineering, Computer Engineering, or Computer Science

M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Synthesis tools

Static timing analysis

Linting tools

Clock domain crossing tools

Logical equivalence checking tools

HDL simulators/EDA tools

Git

Job description

SambaNova RTL Design Engineers design components of the Reconfigurable Dataflow Unit (RDU) ASICs behind our AI acceleration systems. You'll own blocks within a larger subsystem, contributing sections of the microarchitecture specification and carrying your blocks through implementation and silicon bring-up.

You will work alongside principal engineers, architects, design verification, and physical design teams, taking on larger blocks as you deepen your architectural knowledge.