Principal RTL Design Architect for AI Accelerator

Socket.dev; Austin (TX); On-site; USD 180,000 - 255,000; Full time

Job summary

SambaNova Systems is seeking a Principal RTL Design Engineer to own the microarchitecture and RTL for the next-generation RDU. You will shepherd blocks from specs through tape-out, owning power, performance, and area decisions while meeting aggressive frequency targets.

The role requires deep SystemVerilog expertise, SVA, and a track record of leading complex ASIC blocks in fast-paced environments. On-site in Austin, TX, with a focus on RTL and EDA excellence.

Qualifications

• B.S. in Electrical/Computer Engineering or Computer Science.
• 7+ years of ASIC RTL design experience.
• Mastery of synthesizable SystemVerilog, including SVA.
• High-frequency design experience with datapath pipelining/retiming.
• Strong foundation in computer architecture and digital logic.
• Ownership of a complex block from microarchitecture to tape-out.
• Experience balancing power, performance, and area under physical constraints.
• Python scripting for design and flow automation.

Responsibilities

• Own microarchitecture and RTL for major RDU block from spec through tape-out.
• Write, integrate, and debug synthesizable SystemVerilog RTL for full chip implementation.
• Own PPA for your area, hitting aggressive frequency targets.
• Drive timing closure and design quality: synthesis, STA, lint, CDC, LEC, assertions.
• Collaborate with verification to define coverage and debug failures.
• Partner with architects and software teams to prototype performance features.
• Contribute to new EDA methodologies in the design flow.
• Mentor junior engineers and set design review direction.

Skills

SystemVerilog

Python scripting

Datapath pipelining

Microarchitecture design

RTL design

Clock domain crossing

Education

Bachelor's in Electrical Engineering / Computer Engineering / Computer Science

Master's or Ph.D. in Electrical Engineering / Computer Engineering / Computer Science

Tools

Synthesis

Static Timing Analysis (STA)

Lint

CDC

LEC

EDA flows

Job description

SambaNova Systems is seeking a Principal RTL Design Engineer to own the microarchitecture and RTL for the next-generation RDU. You will shepherd blocks from specs through tape-out, owning power, performance, and area decisions while meeting aggressive frequency targets.

The role requires deep SystemVerilog expertise, SVA, and a track record of leading complex ASIC blocks in fast-paced environments. On-site in Austin, TX, with a focus on RTL and EDA excellence.