Senior RTL Architect for AI Accelerator Cores

SambaNova; Austin (TX); On-site; USD 180,000 - 255,000; Full time

Benefits offered by this job

Equity

Medical insurance

HSA

Wellbeing benefits

Job summary

SambaNova is seeking a Principal RTL Design Engineer to own the microarchitecture and RTL for the next-generation Reconfigurable Dataflow Unit (RDU). You will oversee blocks from specification to tape-out, balancing power, performance, and area while meeting aggressive frequency targets.

This senior individual contributor role requires delivering high-quality SystemVerilog, managing timing, and collaborating with verification, architects, and software teams to deliver optimized AI acceleration

Qualifications

• B.S. in Electrical Engineering, Computer Engineering, or Computer Science.
• 7+ years of industry experience in ASIC RTL design.
• Mastery of synthesizable SystemVerilog for high-speed, high-performance ASICs.
• High-frequency design experience with datapath pipelining, retiming, and timing targets.
• Foundational knowledge in computer architecture and digital logic design.
• Ownership of a complex block from microarchitecture through tape-out on a production ASIC.
• Experience merging power, performance, and area with physical constraints.
• Hands-on synthesis, static timing analysis, lint, CDC, and LEC workflows.
• Leadership in design reviews and mentoring engineers.
• Python scripting for design and flow automation.

Responsibilities

• Own microarchitecture and RTL for a major block or subsystem of the RDU from spec to tape-out.
• Write, integrate, and debug synthesizable SystemVerilog RTL through full chip flow.
• Own PPA for your area and hit aggressive frequency targets.
• Drive timing closure and design quality via synthesis, STA, lint, CDC, LEC, and SVAs.
• Partner with verification to define intent and coverage for your block.
• Collaborate with architects and software teams to prototype performance improvements.
• Advance AI, automation, and new EDA methodologies in the design flow.
• Set technical standards in design reviews and mentor engineers.

Skills

SystemVerilog

RTL design

Python

Scripting

PPA optimization

Design reviews

Education

B.S. in Electrical/Computer Engineering or CS

M.S. or Ph.D. preferred

Tools

AXI

PCIe

Ethernet

HBM

DDR

Job description

SambaNova is seeking a Principal RTL Design Engineer to own the microarchitecture and RTL for the next-generation Reconfigurable Dataflow Unit (RDU). You will oversee blocks from specification to tape-out, balancing power, performance, and area while meeting aggressive frequency targets.

This senior individual contributor role requires delivering high-quality SystemVerilog, managing timing, and collaborating with verification, architects, and software teams to deliver optimized AI acceleration