Senior RTL Design Architect – DRAM IP & Low-Power

Micron Technology; Boise (ID); On-site; USD 120,000 - 160,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

Paid family leave

Robust paid time-off program

Paid holidays

Job summary

Micron Technology in Boise, Idaho, is looking for a Principal RTL Design Engineer. You will lead the development of high-quality DRAM digital and mixed-signal IP, managing the full RTL design lifecycle to achieve power, performance, and area targets. Candidates should have strong experience in pre-silicon RTL design, ASIC low-power design methodologies, and proficiency in Verilog/SystemVerilog. Micron offers a robust benefits program and promotes a diverse and inclusive workplace.

Qualifications

• 8+ years of experience in pre-silicon RTL design.
• Ownership of complex RTL/IP development.
• In-depth knowledge of RTL design, logic synthesis, functional verification, and STA.

Responsibilities

• Drive RTL design for DRAM digital and mixed-signal IP.
• Architect high-performance RTL designs aligned with product requirements.
• Collaborate with teams for timing closure and PPA goals.

Skills

RTL design

Logic design

Verilog/SystemVerilog

ASIC low-power design methodologies

Functional verification

Education

Master’s degree in Electrical Engineering

Bachelor’s degree in Electrical Engineering

Tools

Synthesis tools

Simulation tools

Job description

Micron Technology in Boise, Idaho, is looking for a Principal RTL Design Engineer. You will lead the development of high-quality DRAM digital and mixed-signal IP, managing the full RTL design lifecycle to achieve power, performance, and area targets. Candidates should have strong experience in pre-silicon RTL design, ASIC low-power design methodologies, and proficiency in Verilog/SystemVerilog. Micron offers a robust benefits program and promotes a diverse and inclusive workplace.