Senior RTL Design Engineer - High-Performance DRAM

Micron Memory Malaysia Sdn Bhd; Boise, Northern (ID, KY); Hybrid; USD 110,000 - 160,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time-off

Paid holidays

Job summary

Micron Technology is seeking a Senior RTL Engineer in Boise to build and develop DRAM digital and mixed-signal blocks, supporting RTL lifecycle from specification through signoff. You will work with cross-functional teams to meet PPA targets in a collaborative engineering environment.

Qualifications include a master’s degree in EE with 4+ years of experience (or bachelor’s with 5+ years) and hands-on ASIC low-power design experience, UPF, CDC/RDC, and strong Verilog/SystemVerilog proficiency.

Qualifications

• Master’s degree in Electrical Engineering with 4+ years of experience, or Bachelor’s degree with 5+ years of pre-silicon RTL design experience.
• Hands-on experience with ASIC low-power design methodologies, including UPF-based power intent and CDC/RDC analysis.
• Strong knowledge of ASIC design flows, including RTL design, logic synthesis, verification, and static timing analysis.

Responsibilities

• Contribute to RTL build of digital and mixed-signal components for DRAM using RTL-to-GDS flows.
• Implement and document high-performance, power- and area-efficient RTL designs meeting product specifications.
• Perform front-end quality checks including lint, CDC/RDC, synthesis, UPF, and timing QoR.
• Collaborate with physical design and implementation teams to achieve timing closure and PPA goals.
• Apply power-, clock-, and implementation-aware RTL design practices to minimize silicon risk.

Skills

RTL design

Verilog/SystemVerilog

ASIC flows

Synthesis & STA

UPF power intent

CDC/RDC analysis

RTL verification

Education

Master’s degree in Electrical Engineering

Bachelor’s degree

Tools

ASIC design tools

RTL simulation tools

Job description

Micron Technology is seeking a Senior RTL Engineer in Boise to build and develop DRAM digital and mixed-signal blocks, supporting RTL lifecycle from specification through signoff. You will work with cross-functional teams to meet PPA targets in a collaborative engineering environment.

Qualifications include a master’s degree in EE with 4+ years of experience (or bachelor’s with 5+ years) and hands-on ASIC low-power design experience, UPF, CDC/RDC, and strong Verilog/SystemVerilog proficiency.