Senior RTL Design Architect - DRAM IP & Signoff

Micron Memory Malaysia Sdn Bhd; Boise (ID); On-site; USD 140,000 - 210,000; Full time

Job summary

Micron Technology in Boise, Idaho is seeking a Principal RTL Design Engineer to lead the development of high-quality DRAM digital and mixed-signal IP. You will own RTL design from architecture to silicon signoff, targeting best-in-class power, performance, and area.

Collaborate with physical design, verification, and architecture teams to meet aggressive PPA goals, drive automation, and advance RTL design methodologies while mentoring teams across global sites and delivering results.

Qualifications

• 8+ years of pre-silicon RTL design experience with ownership of complex RTL/IP.
• Strong background in ASIC low-power design methodologies using UPF-based power intent.
• Experience collaborating with physical design, verification, and architecture teams.
• Proven ability to drive RTL design from specification through signoff.

Responsibilities

• Own and drive RTL design for DRAM digital and mixed-signal IP from specification through silicon-ready signoff.
• Architect and deliver high-performance, power- and area-efficient RTL designs aligned with product requirements.
• Perform and sign off front-end quality checks, including lint, CDC/RDC, synthesis, UPF, and timing QoR.
• Collaborate with physical design, verification, and architecture teams to achieve timing closure and PPA goals.
• Improve design quality and efficiency by refining methodologies and design flows.

Skills

RTL design ownership

Technical leadership

Education

Master’s degree in Electrical Engineering

Bachelor’s degree with 10+ years pre-silicon RTL design experience

Tools

Verilog/SystemVerilog

Lint/CDC/RDC

Synthesis

UPF

Timing QoR

STA

Job description

Micron Technology in Boise, Idaho is seeking a Principal RTL Design Engineer to lead the development of high-quality DRAM digital and mixed-signal IP. You will own RTL design from architecture to silicon signoff, targeting best-in-class power, performance, and area.

Collaborate with physical design, verification, and architecture teams to meet aggressive PPA goals, drive automation, and advance RTL design methodologies while mentoring teams across global sites and delivering results.