Lead DRAM RTL Design Engineer - PPA Mastery

Micron Technology; Boise (ID); On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

Medical plans

Dental plans

Vision plans

Paid time off

Paid holidays

Job summary

Micron Technology is seeking a Principal RTL Design Engineer to lead the RTL design lifecycle for DRAM IP, from architecture through signoff, at our Boise, Idaho site. You will drive high-performance, power- and area-efficient RTL solutions and partner with physical design, verification, and architecture teams to meet tight PPA targets.

The role requires strong Verilog/SystemVerilog skills, ASIC low-power experience (UPF), and a track record of pre-silicon RTL/IP ownership.

Qualifications

• Master’s degree in Electrical Engineering with 8+ years of RTL design experience.
• Proven ownership of complex RTL/IP development from micro-architecture definition through handoff to physical design.
• Strong experience with ASIC low-power design methodologies including UPF-based power intent and power-aware CDC/RDC.
• In-depth knowledge of RTL design, logic synthesis, functional verification, and STA.

Responsibilities

• Own and drive RTL design for DRAM digital and mixed-signal IP from specification through silicon-ready signoff.
• Architect and deliver high-performance, power- and area-efficient RTL designs aligned with product requirements.
• Perform and sign off front-end quality checks, including lint, CDC/RDC, synthesis, UPF, and timing QoR.
• Collaborate closely with physical design, verification, and architecture teams to achieve timing closure and PPA goals.
• Improve design quality and efficiency by refining methodologies and enhancing RTL design flows.

Skills

RTL design

Verilog

SystemVerilog

low-power design

CDC/RDC

timing analysis

front-end quality checks

leadership

Education

Master’s degree in Electrical Engineering

Bachelor’s degree in Electrical Engineering

Tools

Synthesis tools

front-end simulation tools

Job description

Micron Technology is seeking a Principal RTL Design Engineer to lead the RTL design lifecycle for DRAM IP, from architecture through signoff, at our Boise, Idaho site. You will drive high-performance, power- and area-efficient RTL solutions and partner with physical design, verification, and architecture teams to meet tight PPA targets.

The role requires strong Verilog/SystemVerilog skills, ASIC low-power experience (UPF), and a track record of pre-silicon RTL/IP ownership.