Senior RTL Design Engineer — High-Performance Memory

Micron Technology, Inc.; Boise (ID); On-site; USD 110,000 - 160,000; Full time

Benefits offered by this job

Medical plans

Dental plans

Vision plans

Paid time off

Paid holidays

Job summary

Micron Technology, Inc. in Boise is seeking a Senior Digital Design Engineer to contribute to the development of advanced DRAM digital and mixed‑signal blocks. You will own RTL design, synthesis, timing analysis, and PPA optimization across the RTL‑to‑GDS flow.

Collaborate with architecture, verification, and physical design teams to deliver high‑performance, power-efficient designs that meet product specifications. Strong emphasis on design quality and efficient methodologies.

Qualifications

• Master’s degree in Electrical Engineering with 4+ years of experience, or Bachelor’s degree with 5+ years in digital ASIC/RTL design.
• Experience developing RTL for complex digital designs from specification through implementation handoff.
• Strong knowledge of ASIC front-end design flows including RTL design, functional verification, logic synthesis, CDC/RDC analysis, and static timing analysis (STA).
• Experience developing and maintaining design constraints (SDC), including clocks, timing exceptions, I/O constraints, and multi‑mode multi‑corner timing scenarios.
• Proficiency with Verilog/SystemVerilog and industry‑standard simulation tools.
• Experience with low‑power design methodologies, UPF‑based power intent, timing constraints, and PPA optimization.

Responsibilities

• Design, develop, and deliver RTL for complex DRAM digital and mixed‑signal blocks, ensuring alignment with product specifications and performance targets.
• Perform front-end design quality checks including linting, CDC/RDC analysis, logic synthesis, timing constraint development, and timing closure activities.
• Collaborate with architecture, verification, and physical design teams to optimize power, performance, area (PPA), and overall design quality.
• Develop and maintain synthesis and timing constraints (SDC), analyze timing reports, and drive timing closure across multiple operating scenarios.
• Improve design methodologies, automation, and RTL‑to‑GDS flows to enhance development efficiency, design quality, and time‑to‑market.

Skills

RTL design

Verilog/SystemVerilog

Synthesis

Timing analysis

CDC/RDC analysis

PPA optimization

Linting

Power optimization

Education

Master's degree in Electrical Engineering

Bachelor's degree in Electrical Engineering

Tools

Simulation tools

Job description

Micron Technology, Inc. in Boise is seeking a Senior Digital Design Engineer to contribute to the development of advanced DRAM digital and mixed‑signal blocks. You will own RTL design, synthesis, timing analysis, and PPA optimization across the RTL‑to‑GDS flow.

Collaborate with architecture, verification, and physical design teams to deliver high‑performance, power-efficient designs that meet product specifications. Strong emphasis on design quality and efficient methodologies.