Senior RFIC Layout Engineer for Starshield Silicon

SpaceX; Hawthorne (CA); On-site; USD 140,000 - 205,000; Full time

Benefits offered by this job

Stock options

Medical, vision, and dental coverage

401(k) retirement plan

Paid parental leave

Paid vacation and holidays

Job summary

SpaceX is seeking a Sr. RFIC Layout Designer for the Starshield Silicon program.

You will lead the discipline of layout for analog and RFIC designs, collaborating with chip designers and cross-functional teams to deliver high-performance IC blocks for space and ground applications. You will work on advanced node layouts (16nm/7nm/5nm or below), optimize for noise, matching, and parasitics, and guide layout validation, DRC/ERC, and tape-out readiness while contributing to a challenging

Qualifications

• Bachelor’s degree in electrical or computer engineering or 8+ years of professional IC layout experience.
• 5+ years of professional experience as an IC layout designer.

Responsibilities

• Determine chip floor plan and power/ground distribution strategies.
• Estimate layout schedule and identify complex areas for early investigation.
• Layout of analog/RF circuits with attention to matching and parasitics.
• Perform DRC/ER/ LVS checks and rectify errors.
• Top-level layout integration with ESD structures, pad assembly, and tape-out readiness.
• Collaborate with EDA vendors to trial new tools and features.
• Create guides and demos to share layout techniques.

Skills

Analog layout

RF layout

High-frequency design

Scripting (Python/Perl)

Linux

Version control

Circuit design

Device matching/noise isolation

Communication skills

Independent work

Education

Bachelor’s degree in electrical or computer engineering

8+ years IC layout experience in lieu of degree

Tools

Python

Perl

Shell scripting

Linux

Version control

Job description

SpaceX is seeking a Sr. RFIC Layout Designer for the Starshield Silicon program.

You will lead the discipline of layout for analog and RFIC designs, collaborating with chip designers and cross-functional teams to deliver high-performance IC blocks for space and ground applications. You will work on advanced node layouts (16nm/7nm/5nm or below), optimize for noise, matching, and parasitics, and guide layout validation, DRC/ERC, and tape-out readiness while contributing to a challenging