Senior RFIC Layout Engineer for Space Silicon

United States Digital Space LLC; Hawthorne (CA); On-site; USD 140,000 - 205,000; Full time

Benefits offered by this job

Stock options

Comprehensive medical coverage

Job summary

United States Digital Space LLC is seeking a Sr. RFIC Layout Designer for the Starshield Silicon program.

You will lead the discipline of RFIC layout, collaborating with RFIC designers on full-chip layouts of analog and RFIC blocks for space and ground infrastructure. The role involves working with cross-disciplinary teams, advancing node complexities, and ensuring manufacturability and high-frequency performance up to 50 GHz.

Qualifications

• Bachelor’s degree in electrical or computer engineering or 8+ years of IC layout experience in lieu of a degree.
• 5+ years of professional experience as an IC layout designer.
• Ability to work long hours and weekends to support milestones.

Responsibilities

• Determine chip floor plan with emphasis on power and ground distribution.
• Estimate layout schedule and identify complex areas early.
• Layout of custom RF and analog blocks with matching and parasitic minimization.
• Design rule checks, electrical rule checks, LVS and DRC resolution.
• Top-level layout integration with ESD structures and pad assembly; tape out.
• Collaborate with EDA vendors to trial new tools and features.
• Create guides and demos to share layout techniques with the team.

Skills

Analog layout

IC layout design

High-frequency RF layouts

RF blocks (LNA/VO, mixers)

Linux

Shell scripting

Python

Perl

Version control

Circuit design

Device matching/noise isolation

Excellent communication

Education

Bachelor’s degree in electrical or computer engineering

Tools

Python

Perl

Shell scripting

Linux

Job description

United States Digital Space LLC is seeking a Sr. RFIC Layout Designer for the Starshield Silicon program.

You will lead the discipline of RFIC layout, collaborating with RFIC designers on full-chip layouts of analog and RFIC blocks for space and ground infrastructure. The role involves working with cross-disciplinary teams, advancing node complexities, and ensuring manufacturability and high-frequency performance up to 50 GHz.