Senior RFIC Layout Engineer – Starshield Silicon

InvestedintheMission; Hawthorne (CA); On-site; USD 140,000 - 205,000; Full time

Job summary

SpaceX is seek­ing a Sr. RFIC Layout Designer for the Starshield Silicon team to advance mixed-signal IC layouts in support of national security applications.

The role focuses on full-chip RF/analog layout, floorplanning, and collaboration with RFIC designers on high‑end processes for space hardware. The candidate will work with cross‑disciplinary teams, manage layout schedules, and ensure robust design practices from floor plan to tape-out, including EDA tool evaluation and manufacturability

Qualifications

• Bachelor’s degree in electrical or computer engineering or 8+ years of professional experience with integrated circuit layout.
• 5+ years of professional experience as an IC layout designer.

Responsibilities

• Determine the chip floor plan and power/ground distribution with input from packaging engineers.
• Accurately estimate the layout schedule and identify complex areas for early investigation.
• Layout RF and analog blocks with emphasis on matching and minimizing parasitic capacitance.
• Perform DRC, ERC and LVS checks and resolve errors.
• Coordinate with EDA vendors to trial new tools and features.

Skills

Strong analog layout skills

Experience with RFIC/mixed signal

Excellent communication skills

Independent problem solving

Education

Bachelor’s degree in electrical or computer engineering

8+ years of professional experience in lieu of a degree

Tools

Python

Linux

Shell scripting

Job description

SpaceX is seek­ing a Sr. RFIC Layout Designer for the Starshield Silicon team to advance mixed-signal IC layouts in support of national security applications.

The role focuses on full-chip RF/analog layout, floorplanning, and collaboration with RFIC designers on high‑end processes for space hardware. The candidate will work with cross‑disciplinary teams, manage layout schedules, and ensure robust design practices from floor plan to tape-out, including EDA tool evaluation and manufacturability